Commit 91484aeb authored Apr 02, 2021 by Weihang Li Committed by Zheng Zengkai Jul 20, 2021

RDMA/hns: Avoid enabling RQ inline on UD

mainline inclusion
from mainline-v5.12-rc1
commit 24f3f1cd
category: feature
bugzilla: 174002
CVE:NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=24f3f1cd515447207c339f8981d8a709bd949011

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RQ inline is not supported on UD/GSI QP, it should be disabled in QPC.

Link: https://lore.kernel.org/r/1617354454-47840-2-git-send-email-liweihang@huawei.com


Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: wangsirong <wangsirong@huawei.com>
Reviewed-by: ChunZhi Hu <huchunzhi@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>

parent 7e13c418

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -4113,8 +4113,11 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
		((u32)hr_qp->rdb.dma) >> 1);
		context->rq_db_record_addr = cpu_to_le32(hr_qp->rdb.dma >> 32);

		roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
		(hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
		if (ibqp->qp_type != IB_QPT_UD && ibqp->qp_type != IB_QPT_GSI)
		roce_set_bit(context->byte_76_srqn_op_en,
		V2_QPC_BYTE_76_RQIE_S,
		!!(hr_dev->caps.flags &
		HNS_ROCE_CAP_FLAG_RQ_INLINE));

		roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
		V2_QPC_BYTE_80_RX_CQN_S, get_cqn(ibqp->recv_cq));

drivers/infiniband/hw/hns/hns_roce_qp.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -487,7 +487,9 @@ static int set_rq_size(struct hns_roce_dev hr_dev, struct ib_qp_cap cap,
		hr_qp->rq.max_gs);

		hr_qp->rq.wqe_cnt = cnt;
		if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
		if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE &&
		hr_qp->ibqp.qp_type != IB_QPT_UD &&
		hr_qp->ibqp.qp_type != IB_QPT_GSI)
		hr_qp->rq_inl_buf.wqe_cnt = cnt;
		else
		hr_qp->rq_inl_buf.wqe_cnt = 0;