Commit 91462afa authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.0-2022-09-29' of... 

Merge tag 'amd-drm-fixes-6.0-2022-09-29' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.0-2022-09-29:

amdgpu:
- GC 11.x fixes
- SMU 13.x fixes
- DCN 3.1.4 fixes
- DCN 3.2.x fixes
- GC 9.x fix
- Fence fix
- SR-IOV supend/resume fix
- PSR regression fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220929144003.8363-1-alexander.deucher@amd.com
parents 153a97b4 83ca5fb4

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+4 −0
Original line number Diff line number Diff line
@@ -1050,6 +1050,10 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) 
{

	if (adev->flags & AMD_IS_APU)

		return false;



	if (amdgpu_sriov_vf(adev))

		return false;



	return pm_suspend_target_state != PM_SUSPEND_TO_IDLE;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+26 −1
Original line number Diff line number Diff line
@@ -3152,7 +3152,8 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) 
			continue;

		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {

		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||

		    (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {



			r = adev->ip_blocks[i].version->funcs->resume(adev);

			if (r) {
@@ -4064,12 +4065,20 @@ static void amdgpu_device_evict_resources(struct amdgpu_device *adev) 
int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)

{

	struct amdgpu_device *adev = drm_to_adev(dev);

	int r = 0;



	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)

		return 0;



	adev->in_suspend = true;



	if (amdgpu_sriov_vf(adev)) {

		amdgpu_virt_fini_data_exchange(adev);

		r = amdgpu_virt_request_full_gpu(adev, false);

		if (r)

			return r;

	}



	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))

		DRM_WARN("smart shift update failed\n");
@@ -4093,6 +4102,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) 


	amdgpu_device_ip_suspend_phase2(adev);



	if (amdgpu_sriov_vf(adev))

		amdgpu_virt_release_full_gpu(adev, false);



	return 0;

}
@@ -4111,6 +4123,12 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 
	struct amdgpu_device *adev = drm_to_adev(dev);

	int r = 0;



	if (amdgpu_sriov_vf(adev)) {

		r = amdgpu_virt_request_full_gpu(adev, true);

		if (r)

			return r;

	}



	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)

		return 0;
@@ -4125,6 +4143,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) 
	}



	r = amdgpu_device_ip_resume(adev);



	/* no matter what r is, always need to properly release full GPU */

	if (amdgpu_sriov_vf(adev)) {

		amdgpu_virt_init_data_exchange(adev);

		amdgpu_virt_release_full_gpu(adev, true);

	}



	if (r) {

		dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);

		return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+0 −1
Original line number Diff line number Diff line
@@ -400,7 +400,6 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 
	/* We are not protected by ring lock when reading the last sequence

	 * but it's ok to report slightly wrong fence count here.

	 */

	amdgpu_fence_process(ring);

	emitted = 0x100000000ull;

	emitted -= atomic_read(&ring->fence_drv.last_seq);

	emitted += READ_ONCE(ring->fence_drv.sync_seq);

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+2 −0
Original line number Diff line number Diff line
@@ -222,6 +222,8 @@ struct mes_add_queue_input { 
	uint64_t	tba_addr;

	uint64_t	tma_addr;

	uint32_t	is_kfd_process;

	uint32_t	is_aql_queue;

	uint32_t	queue_size;

};



struct mes_remove_queue_input {

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+4 −0
Original line number Diff line number Diff line
@@ -5260,6 +5260,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
{

	u32 reg, data;



	amdgpu_gfx_off_ctrl(adev, false);



	reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(reg);
@@ -5273,6 +5275,8 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
		WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);



	amdgpu_gfx_off_ctrl(adev, true);

}



static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {