Commit 9113a0fb authored by Guchun Chen's avatar Guchun Chen Committed by Alex Deucher
Browse files

drm/amd/pm: fix gpu reset failure by MP1 state setting 



Instead of blocking varied unsupported MP1 state in upper level,
defer and skip such MP1 state handling in specific ASIC.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c93ebea0

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

+0 −3
Original line number Diff line number Diff line
@@ -1027,9 +1027,6 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 
	int ret = 0;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;



	if (mp1_state == PP_MP1_STATE_NONE)

		return 0;



	if (pp_funcs && pp_funcs->set_mp1_state) {

		ret = pp_funcs->set_mp1_state(

				adev->powerplay.pp_handle,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+7 −3
Original line number Diff line number Diff line
@@ -3113,14 +3113,18 @@ static int sienna_cichlid_system_features_control(struct smu_context *smu, 
static int sienna_cichlid_set_mp1_state(struct smu_context *smu,

					enum pp_mp1_state mp1_state)

{

	int ret;



	switch (mp1_state) {

	case PP_MP1_STATE_UNLOAD:

		return smu_cmn_set_mp1_state(smu, mp1_state);

		ret = smu_cmn_set_mp1_state(smu, mp1_state);

		break;

	default:

		return -EINVAL;

		/* Ignore others */

		ret = 0;

	}



	return 0;

	return ret;

}



static const struct pptable_funcs sienna_cichlid_ppt_funcs = {