Commit 91123b37 authored by Xiaochen Shen's avatar Xiaochen Shen Committed by Vinod Koul
Browse files

dmaengine: idxd: Make max batch size attributes in sysfs invisible for Intel IAA

In current code, dev.max_batch_size and wq.max_batch_size attributes in
sysfs are exposed to user to show or update the values.

>From Intel IAA spec [1], Intel IAA does not support batch processing. So
these sysfs attributes should not be supported on IAA device.

Fix this issue by making the attributes of max_batch_size invisible in
sysfs through is_visible() filter when the device is IAA.

Add description in the ABI documentation to mention that the attributes
are not visible when the device does not support batch.

[1]: https://cdrdv2.intel.com/v1/dl/getContent/721858



Fixes: e7184b15 ("dmaengine: idxd: add support for configurable max wq batch size")
Fixes: c52ca478 ("dmaengine: idxd: add configuration component of driver")
Signed-off-by: default avatarXiaochen Shen <xiaochen.shen@intel.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20220930201528.18621-3-xiaochen.shen@intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent c3b63380
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+2 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Date: Oct 25, 2019
KernelVersion:  5.6.0
Contact:        dmaengine@vger.kernel.org
Description:    The largest number of work descriptors in a batch.
                It's not visible when the device does not support batch.

What:           /sys/bus/dsa/devices/dsa<m>/max_work_queues_size
Date:           Oct 25, 2019
@@ -205,6 +206,7 @@ KernelVersion: 5.10.0
Contact:	dmaengine@vger.kernel.org
Description:	The max batch size for this workqueue. Cannot exceed device
		max batch size. Configurable parameter.
		It's not visible when the device does not support batch.

What:		/sys/bus/dsa/devices/wq<m>.<n>/ats_disable
Date:		Nov 13, 2020
+32 −0
Original line number Diff line number Diff line
@@ -1233,6 +1233,14 @@ static bool idxd_wq_attr_op_config_invisible(struct attribute *attr,
	       !idxd->hw.wq_cap.op_config;
}

static bool idxd_wq_attr_max_batch_size_invisible(struct attribute *attr,
						  struct idxd_device *idxd)
{
	/* Intel IAA does not support batch processing, make it invisible */
	return attr == &dev_attr_wq_max_batch_size.attr &&
	       idxd->data->type == IDXD_TYPE_IAX;
}

static umode_t idxd_wq_attr_visible(struct kobject *kobj,
				    struct attribute *attr, int n)
{
@@ -1243,6 +1251,9 @@ static umode_t idxd_wq_attr_visible(struct kobject *kobj,
	if (idxd_wq_attr_op_config_invisible(attr, idxd))
		return 0;

	if (idxd_wq_attr_max_batch_size_invisible(attr, idxd))
		return 0;

	return attr->mode;
}

@@ -1533,6 +1544,26 @@ static ssize_t cmd_status_store(struct device *dev, struct device_attribute *att
}
static DEVICE_ATTR_RW(cmd_status);

static bool idxd_device_attr_max_batch_size_invisible(struct attribute *attr,
						      struct idxd_device *idxd)
{
	/* Intel IAA does not support batch processing, make it invisible */
	return attr == &dev_attr_max_batch_size.attr &&
	       idxd->data->type == IDXD_TYPE_IAX;
}

static umode_t idxd_device_attr_visible(struct kobject *kobj,
					struct attribute *attr, int n)
{
	struct device *dev = container_of(kobj, struct device, kobj);
	struct idxd_device *idxd = confdev_to_idxd(dev);

	if (idxd_device_attr_max_batch_size_invisible(attr, idxd))
		return 0;

	return attr->mode;
}

static struct attribute *idxd_device_attributes[] = {
	&dev_attr_version.attr,
	&dev_attr_max_groups.attr,
@@ -1560,6 +1591,7 @@ static struct attribute *idxd_device_attributes[] = {

static const struct attribute_group idxd_device_attribute_group = {
	.attrs = idxd_device_attributes,
	.is_visible = idxd_device_attr_visible,
};

static const struct attribute_group *idxd_attribute_groups[] = {