Commit 910ab9ee authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: only init tap_delay ucode when it's included in ucode binary 



Not all the gfx10 variants need to integrate
global tap_delay and per se tap_delay firmwares

Only init tap_delay ucode when it does include in
rlc ucode binary so driver doesn't send a null buffer
to psp for firmware loading

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJack Gui <Jack.Gui@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7b471c32

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+35 −25
Original line number Diff line number Diff line
@@ -4274,35 +4274,45 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 


		}



		if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {

			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];

			info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;

			info->fw = adev->gfx.rlc_fw;

			adev->firmware.fw_size +=

				ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);

		}



		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];

		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;