Unverified Commit 90f5514b authored by Liu Ying's avatar Liu Ying Committed by Robert Foss
Browse files

drm/bridge: fsl-ldb: Fix mode clock rate validation 



With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.

Fixes: 463db5c2 ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge")
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220701065634.4027537-2-victor.liu@nxp.com
parent 47a4fb46

drivers/gpu/drm/bridge/fsl-ldb.c

+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, 
{

	struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);



	if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000))

	if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))

		return MODE_CLOCK_HIGH;



	return MODE_OK;