Unverified Commit 90e0d94d authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge tag 'dt-for-palmer-v6.1-mw1' of... 

Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into for-next

Microchip RISC-V devicetrees for v6.1

Fixups, reference design changes and new boards:
- The addition of QSPI support for mpfs had a corresponding change to
  the devicetree node.
- The v2022.{09,10} reference designs brought with them several memory
  map changes which are not backwards compatible. The old devicetrees
  from the v2022.08 and earlier releases still work with current
  kernels.
- Two new devicetrees for a first-party development kit and for the
  Aries Embedded M100FPSEVP kit.
- Corresponding dt-bindings changes for the above.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

:
  riscv: dts: microchip: fix fabric i2c reg size
  riscv: dts: microchip: update memory configuration for v2022.10
  riscv: dts: microchip: add a devicetree for aries' m100pfsevp
  riscv: dts: microchip: add sevkit device tree
  riscv: dts: microchip: reduce the fic3 clock rate
  riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
  riscv: dts: microchip: icicle: update pci address properties
  riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
  riscv: dts: microchip: add pci dma ranges for the icicle kit
  dt-bindings: riscv: microchip: document the sev kit
  dt-bindings: riscv: microchip: document the aries m100pfsevp
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: add qspi compatible fallback

Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 06267eb2 c210b918

Documentation/devicetree/bindings/riscv/microchip.yaml

+14 −6
Original line number Diff line number Diff line
@@ -17,10 +17,18 @@ properties: 
  $nodename:

    const: '/'

  compatible:

    items:

    oneOf:

      - items:

          - enum:

          - microchip,mpfs-icicle-kit

              - microchip,mpfs-icicle-reference-rtlv2203

              - microchip,mpfs-icicle-reference-rtlv2210

          - const: microchip,mpfs-icicle-kit

          - const: microchip,mpfs



      - items:

          - enum:

              - aries,m100pfsevp

              - microchip,mpfs-sev-kit

              - sundance,polarberry

          - const: microchip,mpfs

arch/riscv/boot/dts/microchip/Makefile

+2 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb

dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb

obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

+37 −6
Original line number Diff line number Diff line
@@ -2,20 +2,21 @@ 
/* Copyright (c) 2020-2021 Microchip Technology Inc */



/ {

	compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";

	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",

		     "microchip,mpfs";



	core_pwm0: pwm@41000000 {

	core_pwm0: pwm@40000000 {

		compatible = "microchip,corepwm-rtl-v4";

		reg = <0x0 0x41000000 0x0 0xF0>;

		reg = <0x0 0x40000000 0x0 0xF0>;

		microchip,sync-update-mask = /bits/ 32 <0>;

		#pwm-cells = <2>;

		clocks = <&fabric_clk3>;

		status = "disabled";

	};



	i2c2: i2c@44000000 {

	i2c2: i2c@40000200 {

		compatible = "microchip,corei2c-rtl-v7";

		reg = <0x0 0x44000000 0x0 0x1000>;

		reg = <0x0 0x40000200 0x0 0x100>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&fabric_clk3>;
@@ -28,7 +29,7 @@ 
	fabric_clk3: fabric-clk3 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <62500000>;

		clock-frequency = <50000000>;

	};



	fabric_clk1: fabric-clk1 {
@@ -36,4 +37,34 @@ 
		#clock-cells = <0>;

		clock-frequency = <125000000>;

	};



	pcie: pcie@3000000000 {

		compatible = "microchip,pcie-host-1.0";

		#address-cells = <0x3>;

		#interrupt-cells = <0x1>;

		#size-cells = <0x2>;

		device_type = "pci";

		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;

		reg-names = "cfg", "apb";

		bus-range = <0x0 0x7f>;

		interrupt-parent = <&plic>;

		interrupts = <119>;

		interrupt-map = <0 0 0 1 &pcie_intc 0>,

				<0 0 0 2 &pcie_intc 1>,

				<0 0 0 3 &pcie_intc 2>,

				<0 0 0 4 &pcie_intc 3>;

		interrupt-map-mask = <0 0 0 7>;

		clocks = <&fabric_clk1>, <&fabric_clk3>;

		clock-names = "fic1", "fic3";

		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;

		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;

		msi-parent = <&pcie>;

		msi-controller;

		status = "disabled";

		pcie_intc: interrupt-controller {

			#address-cells = <0>;

			#interrupt-cells = <1>;

			interrupt-controller;

		};

	};

};

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+15 −3
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ 


/ {

	model = "Microchip PolarFire-SoC Icicle Kit";

	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",

		     "microchip,mpfs";



	aliases {

		ethernet0 = &mac1;
@@ -32,15 +33,26 @@ 


	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x2e000000>;

		reg = <0x0 0x80000000 0x0 0x40000000>;

		status = "okay";

	};



	ddrc_cache_hi: memory@1000000000 {

		device_type = "memory";

		reg = <0x10 0x0 0x0 0x40000000>;

		reg = <0x10 0x40000000 0x0 0x40000000>;

		status = "okay";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		hss_payload: region@BFC00000 {

			reg = <0x0 0xBFC00000 0x0 0x400000>;

			no-map;

		};

	};

};



&core_pwm0 {

arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi

0 → 100644
+45 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2022 Microchip Technology Inc */



/ {

	fabric_clk3: fabric-clk3 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <62500000>;

	};



	fabric_clk1: fabric-clk1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <125000000>;

	};



	pcie: pcie@2000000000 {

		compatible = "microchip,pcie-host-1.0";

		#address-cells = <0x3>;

		#interrupt-cells = <0x1>;

		#size-cells = <0x2>;

		device_type = "pci";

		reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;

		reg-names = "cfg", "apb";

		bus-range = <0x0 0x7f>;

		interrupt-parent = <&plic>;

		interrupts = <119>;

		interrupt-map = <0 0 0 1 &pcie_intc 0>,

				<0 0 0 2 &pcie_intc 1>,

				<0 0 0 3 &pcie_intc 2>,

				<0 0 0 4 &pcie_intc 3>;

		interrupt-map-mask = <0 0 0 7>;

		clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;

		clock-names = "fic0", "fic1", "fic3";

		ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;

		msi-parent = <&pcie>;

		msi-controller;

		status = "disabled";

		pcie_intc: interrupt-controller {

			#address-cells = <0>;

			#interrupt-cells = <1>;

			interrupt-controller;

		};

	};

};