Unverified Commit 90ddcd64 authored by Damien Le Moal's avatar Damien Le Moal Committed by Palmer Dabbelt
Browse files

dt-bindings: update sifive plic compatible string 



Add the compatible string "canaan,k210-plic" to the Sifive plic bindings
to indicate the use of the "sifive,plic-1.0.0" IP block in the Canaan
Kendryte K210 SoC. The description is also updated to reflect this
change, that is, that SoCs from other vendors may also use this plic
implementation.

Signed-off-by: default avatarDamien Le Moal <damien.lemoal@wdc.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 7ef71c71

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

+8 −5
Original line number Diff line number Diff line
@@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: SiFive Platform-Level Interrupt Controller (PLIC)



description:

  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller

  (PLIC) high-level specification in the RISC-V Privileged Architecture

  specification. The PLIC connects all external interrupts in the system to all

  hart contexts in the system, via the external interrupt source in each hart.

  SiFive SoCs and other RISC-V SoCs include an implementation of the

  Platform-Level Interrupt Controller (PLIC) high-level specification in

  the RISC-V Privileged Architecture specification. The PLIC connects all

  external interrupts in the system to all hart contexts in the system, via

  the external interrupt source in each hart.



  A hart context is a privilege mode in a hardware execution thread. For example,

  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
@@ -42,7 +43,9 @@ maintainers: 
properties:

  compatible:

    items:

      - const: sifive,fu540-c000-plic

      - enum:

          - sifive,fu540-c000-plic

          - canaan,k210-plic

      - const: sifive,plic-1.0.0



  reg: