Commit 90b593ce authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/adreno: Switch to chip-id for identifying GPU 



Since the revision becomes an opaque identifier with future GPUs, move
away from treating different ranges of bits as having a given meaning.
This means that we need to explicitly list different patch revisions in
the device table.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549782/
parent b42ab854

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);

	/* Early A430's have a timing issue with SP/TP power collapse;

	   disabling HW clock gating prevents it. */

	if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2)

	if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2)

		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);

	else

		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -1770,7 +1770,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) 


	nr_rings = 4;



	if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev))

	if (config->info->revn == 510)

		nr_rings = 1;



	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings);

drivers/gpu/drm/msm/adreno/a5xx_power.c

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu) 


	/* The battery current limiter isn't enabled for A540 */

	config = AGC_LM_CONFIG_BCL_DISABLED;

	config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;

	config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT;



	/* For now disable GPMU side throttling */

	config |= AGC_LM_CONFIG_THROTTLE_DISABLE;

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+10 −4
Original line number Diff line number Diff line
@@ -790,10 +790,16 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 
	gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,

		(1 << 31) | (0xa << 18) | (0xa0));



	chipid = adreno_gpu->rev.core << 24;

	chipid |= adreno_gpu->rev.major << 16;

	chipid |= adreno_gpu->rev.minor << 12;

	chipid |= adreno_gpu->rev.patchid << 8;

	/*

	 * Note that the GMU has a slightly different layout for

	 * chip_id, for whatever reason, so a bit of massaging

	 * is needed.  The upper 16b are the same, but minor and

	 * patchid are packed in four bits each with the lower

	 * 8b unused:

	 */

	chipid  = adreno_gpu->chip_id & 0xffff0000;

	chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */

	chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */



	gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);

drivers/gpu/drm/msm/adreno/adreno_device.c

+70 −67
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); 


static const struct adreno_info gpulist[] = {

	{

		.rev   = ADRENO_REV(2, 0, 0, 0),

		.chip_ids = ADRENO_CHIP_IDS(0x02000000),

		.family = ADRENO_2XX_GEN1,

		.revn  = 200,

		.fw = {
@@ -33,7 +33,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a2xx_gpu_init,

	}, { /* a200 on i.mx51 has only 128kib gmem */

		.rev   = ADRENO_REV(2, 0, 0, 1),

		.chip_ids = ADRENO_CHIP_IDS(0x02000001),

		.family = ADRENO_2XX_GEN1,

		.revn  = 201,

		.fw = {
@@ -44,7 +44,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a2xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(2, 2, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x02020000),

		.family = ADRENO_2XX_GEN2,

		.revn  = 220,

		.fw = {
@@ -55,7 +55,10 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a2xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(3, 0, 5, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(

			0x03000512,

			0x03000520

		),

		.family = ADRENO_3XX,

		.revn  = 305,

		.fw = {
@@ -66,7 +69,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(3, 0, 6, 0),

		.chip_ids = ADRENO_CHIP_IDS(0x03000600),

		.family = ADRENO_3XX,

		.revn  = 307,        /* because a305c is revn==306 */

		.fw = {
@@ -77,7 +80,11 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(

			0x03020000,

			0x03020001,

			0x03020002

		),

		.family = ADRENO_3XX,

		.revn  = 320,

		.fw = {
@@ -88,7 +95,11 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(3, 3, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(

			0x03030000,

			0x03030001,

			0x03030002

		),

		.family = ADRENO_3XX,

		.revn  = 330,

		.fw = {
@@ -99,7 +110,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a3xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(4, 0, 5, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x04000500),

		.family = ADRENO_4XX,

		.revn  = 405,

		.fw = {
@@ -110,7 +121,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a4xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x04020000),

		.family = ADRENO_4XX,

		.revn  = 420,

		.fw = {
@@ -121,7 +132,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a4xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(4, 3, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x04030002),

		.family = ADRENO_4XX,

		.revn  = 430,

		.fw = {
@@ -132,7 +143,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init  = a4xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(5, 0, 6, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05000600),

		.family = ADRENO_5XX,

		.revn = 506,

		.fw = {
@@ -150,7 +161,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a5xx_gpu_init,

		.zapfw = "a506_zap.mdt",

	}, {

		.rev   = ADRENO_REV(5, 0, 8, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05000800),

		.family = ADRENO_5XX,

		.revn = 508,

		.fw = {
@@ -167,7 +178,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a5xx_gpu_init,

		.zapfw = "a508_zap.mdt",

	}, {

		.rev   = ADRENO_REV(5, 0, 9, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05000900),

		.family = ADRENO_5XX,

		.revn = 509,

		.fw = {
@@ -185,7 +196,7 @@ static const struct adreno_info gpulist[] = { 
		/* Adreno 509 uses the same ZAP as 512 */

		.zapfw = "a512_zap.mdt",

	}, {

		.rev   = ADRENO_REV(5, 1, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05010000),

		.family = ADRENO_5XX,

		.revn = 510,

		.fw = {
@@ -200,7 +211,7 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = 250,

		.init = a5xx_gpu_init,

	}, {

		.rev   = ADRENO_REV(5, 1, 2, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05010200),

		.family = ADRENO_5XX,

		.revn = 512,

		.fw = {
@@ -217,7 +228,10 @@ static const struct adreno_info gpulist[] = { 
		.init = a5xx_gpu_init,

		.zapfw = "a512_zap.mdt",

	}, {

		.rev = ADRENO_REV(5, 3, 0, 2),

		.chip_ids = ADRENO_CHIP_IDS(

			0x05030002,

			0x05030004

		),

		.family = ADRENO_5XX,

		.revn = 530,

		.fw = {
@@ -236,7 +250,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a5xx_gpu_init,

		.zapfw = "a530_zap.mdt",

	}, {

		.rev = ADRENO_REV(5, 4, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x05040001),

		.family = ADRENO_5XX,

		.revn = 540,

		.fw = {
@@ -254,7 +268,7 @@ static const struct adreno_info gpulist[] = { 
		.init = a5xx_gpu_init,

		.zapfw = "a540_zap.mdt",

	}, {

		.rev = ADRENO_REV(6, 1, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06010000),

		.family = ADRENO_6XX_GEN1,

		.revn = 610,

		.fw = {
@@ -280,7 +294,7 @@ static const struct adreno_info gpulist[] = { 
			{ 127, 4 },

		),

	}, {

		.rev = ADRENO_REV(6, 1, 8, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06010800),

		.family = ADRENO_6XX_GEN1,

		.revn = 618,

		.fw = {
@@ -298,7 +312,7 @@ static const struct adreno_info gpulist[] = { 
		),

	}, {

		.machine = "qcom,sm4350",

		.rev = ADRENO_REV(6, 1, 9, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06010900),

		.family = ADRENO_6XX_GEN1,

		.revn = 619,

		.fw = {
@@ -317,7 +331,7 @@ static const struct adreno_info gpulist[] = { 
		),

	}, {

		.machine = "qcom,sm6375",

		.rev = ADRENO_REV(6, 1, 9, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06010900),

		.family = ADRENO_6XX_GEN1,

		.revn = 619,

		.fw = {
@@ -335,7 +349,7 @@ static const struct adreno_info gpulist[] = { 
			{ 177, 2 },

		),

	}, {

		.rev = ADRENO_REV(6, 1, 9, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06010900),

		.family = ADRENO_6XX_GEN1,

		.revn = 619,

		.fw = {
@@ -356,7 +370,10 @@ static const struct adreno_info gpulist[] = { 
			{ 180, 1 },

		),

	}, {

		.rev = ADRENO_REV(6, 3, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(

			0x06030001,

			0x06030002

		),

		.family = ADRENO_6XX_GEN1,

		.revn = 630,

		.fw = {
@@ -370,7 +387,7 @@ static const struct adreno_info gpulist[] = { 
		.zapfw = "a630_zap.mdt",

		.hwcg = a630_hwcg,

	}, {

		.rev = ADRENO_REV(6, 4, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06040001),

		.family = ADRENO_6XX_GEN2,

		.revn = 640,

		.fw = {
@@ -388,7 +405,7 @@ static const struct adreno_info gpulist[] = { 
			{ 1, 1 },

		),

	}, {

		.rev = ADRENO_REV(6, 5, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06050002),

		.family = ADRENO_6XX_GEN3,

		.revn = 650,

		.fw = {
@@ -410,7 +427,7 @@ static const struct adreno_info gpulist[] = { 
			{ 3, 2 },

		),

	}, {

		.rev = ADRENO_REV(6, 6, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06060001),

		.family = ADRENO_6XX_GEN4,

		.revn = 660,

		.fw = {
@@ -426,7 +443,7 @@ static const struct adreno_info gpulist[] = { 
		.hwcg = a660_hwcg,

		.address_space_size = SZ_16G,

	}, {

		.rev = ADRENO_REV(6, 3, 5, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06030500),

		.family = ADRENO_6XX_GEN4,

		.fw = {

			[ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -445,7 +462,7 @@ static const struct adreno_info gpulist[] = { 
			{ 190, 1 },

		),

	}, {

		.rev = ADRENO_REV(6, 8, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06080000),

		.family = ADRENO_6XX_GEN2,

		.revn = 680,

		.fw = {
@@ -459,7 +476,7 @@ static const struct adreno_info gpulist[] = { 
		.zapfw = "a640_zap.mdt",

		.hwcg = a640_hwcg,

	}, {

		.rev = ADRENO_REV(6, 9, 0, ANY_ID),

		.chip_ids = ADRENO_CHIP_IDS(0x06090000),

		.family = ADRENO_6XX_GEN4,

		.fw = {

			[ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -494,30 +511,15 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw"); 
MODULE_FIRMWARE("qcom/a630_gmu.bin");

MODULE_FIRMWARE("qcom/a630_zap.mbn");



static inline bool _rev_match(uint8_t entry, uint8_t id)

static const struct adreno_info *adreno_info(uint32_t chip_id)

{

	return (entry == ANY_ID) || (entry == id);

}



bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)

{



	return _rev_match(rev1.core, rev2.core) &&

		_rev_match(rev1.major, rev2.major) &&

		_rev_match(rev1.minor, rev2.minor) &&

		_rev_match(rev1.patchid, rev2.patchid);

}



static const struct adreno_info *adreno_info(struct adreno_rev rev)

{

	int i;



	/* identify gpu: */

	for (i = 0; i < ARRAY_SIZE(gpulist); i++) {

	for (int i = 0; i < ARRAY_SIZE(gpulist); i++) {

		const struct adreno_info *info = &gpulist[i];

		if (info->machine && !of_machine_is_compatible(info->machine))

			continue;

		if (adreno_cmp_rev(info->rev, rev))

		for (int j = 0; info->chip_ids[j]; j++)

			if (info->chip_ids[j] == chip_id)

				return info;

	}
@@ -598,12 +600,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 
	return NULL;

}



static int find_chipid(struct device *dev, struct adreno_rev *rev)

static int find_chipid(struct device *dev, uint32_t *chipid)

{

	struct device_node *node = dev->of_node;

	const char *compat;

	int ret;

	u32 chipid;



	/* first search the compat strings for qcom,adreno-XYZ.W: */

	ret = of_property_read_string_index(node, "compatible", 0, &compat);
@@ -612,32 +613,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev) 


		if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||

		    sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {

			rev->core = r / 100;

			uint32_t core, major, minor;



			core = r / 100;

			r %= 100;

			rev->major = r / 10;

			major = r / 10;

			r %= 10;

			rev->minor = r;

			rev->patchid = patch;

			minor = r;



			*chipid = (core << 24) |

				(major << 16) |

				(minor << 8) |

				patch;



			return 0;

		}



		if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1)

			return 0;

	}



	/* and if that fails, fall back to legacy "qcom,chipid" property: */

	ret = of_property_read_u32(node, "qcom,chipid", &chipid);

	ret = of_property_read_u32(node, "qcom,chipid", chipid);

	if (ret) {

		DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);

		return ret;

	}



	rev->core = (chipid >> 24) & 0xff;

	rev->major = (chipid >> 16) & 0xff;

	rev->minor = (chipid >> 8) & 0xff;

	rev->patchid = (chipid & 0xff);



	dev_warn(dev, "Using legacy qcom,chipid binding!\n");

	dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",

		rev->core, rev->major, rev->minor, rev->patchid);



	return 0;

}
@@ -651,23 +654,23 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) 
	struct msm_gpu *gpu;

	int ret;



	ret = find_chipid(dev, &config.rev);

	ret = find_chipid(dev, &config.chip_id);

	if (ret)

		return ret;



	dev->platform_data = &config;

	priv->gpu_pdev = to_platform_device(dev);



	info = adreno_info(config.rev);

	info = adreno_info(config.chip_id);

	if (!info) {

		dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n",

			ADRENO_CHIPID_ARGS(config.rev));

			ADRENO_CHIPID_ARGS(config.chip_id));

		return -ENXIO;

	}



	config.info = info;



	DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev));

	DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id));



	priv->is_a2xx = info->family < ADRENO_3XX;

	priv->has_cached_coherent =