Commit 907f9291 authored by Eugeniy Paltsev's avatar Eugeniy Paltsev Committed by Stephen Boyd
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CLK: HSDK: CGU: check if PLL is bypassed first 



If PLL is bypassed the EN (enable) bit has no effect on
output clock.

Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-2-Eugeniy.Paltsev@synopsys.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8f3d9f35

drivers/clk/clk-hsdk-pll.c

+4 −4
Original line number Diff line number Diff line
@@ -172,14 +172,14 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw, 


	dev_dbg(clk->dev, "current configuration: %#x\n", val);



	/* Check if PLL is disabled */

	if (val & CGU_PLL_CTRL_PD)

		return 0;



	/* Check if PLL is bypassed */

	if (val & CGU_PLL_CTRL_BYPASS)

		return parent_rate;



	/* Check if PLL is disabled */

	if (val & CGU_PLL_CTRL_PD)

		return 0;



	/* input divider = reg.idiv + 1 */

	idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);

	/* fb divider = 2*(reg.fbdiv + 1) */