Commit 90654da4 authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge tag 'arm-smmu-updates' of... 

Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu

Qualc^WArm SMMU updates for 6.6

- Device-tree binding updates:
  * Add additional compatible strings for Qualcomm SoCs
  * Allow ASIDs to be configured in the DT to work around Qualcomm's
    broken hypervisor
  * Fix clocks for Qualcomm's MSM8998 SoC

- SMMUv2:
  * Support for Qualcomm's legacy firmware implementation featured on
    at least MSM8956 and MSM8976.
  * Match compatible strings for Qualcomm SM6350 and SM6375 SoC variants

- SMMUv3:
  * Use 'ida' instead of a bitmap for VMID allocation
parents 6eaae198 afe92fbf

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+41 −0
Original line number Diff line number Diff line
@@ -270,6 +270,47 @@ allOf: 
          contains:

            enum:

              - qcom,msm8998-smmu-v2

    then:

      anyOf:

        - properties:

            clock-names:

              items:

                - const: bus

            clocks:

              items:

                - description: bus clock required for downstream bus access and for

                    the smmu ptw

        - properties:

            clock-names:

              items:

                - const: iface

                - const: mem

                - const: mem_iface

            clocks:

              items:

                - description: interface clock required to access smmu's registers

                    through the TCU's programming interface.

                - description: bus clock required for memory access

                - description: bus clock required for GPU memory access

        - properties:

            clock-names:

              items:

                - const: iface-mm

                - const: iface-smmu

                - const: bus-smmu

            clocks:

              items:

                - description: interface clock required to access mnoc's registers

                    through the TCU's programming interface.

                - description: interface clock required to access smmu's registers

                    through the TCU's programming interface.

                - description: bus clock required for the smmu ptw



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sdm630-smmu-v2

              - qcom,sm6375-smmu-v2

    then:

Documentation/devicetree/bindings/iommu/qcom,iommu.yaml

+17 −5
Original line number Diff line number Diff line
@@ -17,11 +17,16 @@ description: | 


properties:

  compatible:

    items:

    oneOf:

      - items:

          - enum:

              - qcom,msm8916-iommu

              - qcom,msm8953-iommu

          - const: qcom,msm-iommu-v1

      - items:

          - enum:

              - qcom,msm8976-iommu

          - const: qcom,msm-iommu-v2



  clocks:

    items:
@@ -64,6 +69,8 @@ patternProperties: 
        enum:

          - qcom,msm-iommu-v1-ns

          - qcom,msm-iommu-v1-sec

          - qcom,msm-iommu-v2-ns

          - qcom,msm-iommu-v2-sec



      interrupts:

        maxItems: 1
@@ -71,6 +78,11 @@ patternProperties: 
      reg:

        maxItems: 1



      qcom,ctx-asid:

        $ref: /schemas/types.yaml#/definitions/uint32

        description:

          The ASID number associated to the context bank.



    required:

      - compatible

      - interrupts

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+7 −22
Original line number Diff line number Diff line
@@ -2055,24 +2055,6 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) 
	return &smmu_domain->domain;

}



static int arm_smmu_bitmap_alloc(unsigned long *map, int span)

{

	int idx, size = 1 << span;



	do {

		idx = find_first_zero_bit(map, size);

		if (idx == size)

			return -ENOSPC;

	} while (test_and_set_bit(idx, map));



	return idx;

}



static void arm_smmu_bitmap_free(unsigned long *map, int idx)

{

	clear_bit(idx, map);

}



static void arm_smmu_domain_free(struct iommu_domain *domain)

{

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
@@ -2093,7 +2075,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) 
	} else {

		struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;

		if (cfg->vmid)

			arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid);

			ida_free(&smmu->vmid_map, cfg->vmid);

	}



	kfree(smmu_domain);
@@ -2167,7 +2149,9 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, 
	struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;

	typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr;



	vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits);

	/* Reserve VMID 0 for stage-2 bypass STEs */

	vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1,

			       GFP_KERNEL);

	if (vmid < 0)

		return vmid;
@@ -3098,8 +3082,8 @@ static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) 
	reg |= STRTAB_BASE_RA;

	smmu->strtab_cfg.strtab_base = reg;



	/* Allocate the first VMID for stage-2 bypass STEs */

	set_bit(0, smmu->vmid_map);

	ida_init(&smmu->vmid_map);



	return 0;

}
@@ -3923,6 +3907,7 @@ static void arm_smmu_device_remove(struct platform_device *pdev) 
	iommu_device_sysfs_remove(&smmu->iommu);

	arm_smmu_device_disable(smmu);

	iopf_queue_free(smmu->evtq.iopf);

	ida_destroy(&smmu->vmid_map);

}



static void arm_smmu_device_shutdown(struct platform_device *pdev)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

+1 −1
Original line number Diff line number Diff line
@@ -670,7 +670,7 @@ struct arm_smmu_device { 


#define ARM_SMMU_MAX_VMIDS		(1 << 16)

	unsigned int			vmid_bits;

	DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS);

	struct ida			vmid_map;



	unsigned int			ssid_bits;

	unsigned int			sid_bits;

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

+5 −2
Original line number Diff line number Diff line
@@ -251,10 +251,12 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { 
	{ .compatible = "qcom,sc7280-mss-pil" },

	{ .compatible = "qcom,sc8180x-mdss" },

	{ .compatible = "qcom,sc8280xp-mdss" },

	{ .compatible = "qcom,sm8150-mdss" },

	{ .compatible = "qcom,sm8250-mdss" },

	{ .compatible = "qcom,sdm845-mdss" },

	{ .compatible = "qcom,sdm845-mss-pil" },

	{ .compatible = "qcom,sm6350-mdss" },

	{ .compatible = "qcom,sm6375-mdss" },

	{ .compatible = "qcom,sm8150-mdss" },

	{ .compatible = "qcom,sm8250-mdss" },

	{ }

};
@@ -528,6 +530,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { 
	{ .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm6375-smmu-v2", .data = &qcom_smmu_v2_data },

	{ .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data },

	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },