Commit 90515a45 authored by Jia He's avatar Jia He
Browse files

arm64: Subscribe Microsoft Azure Cobalt 100 to erratum 3194386 

mainline inclusion
from mainline-v6.12-rc2
commit 3eddb108abe3de6723cc4b77e8558ce1b3047987
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB3K2H
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3eddb108abe3



------------------------------------

Signed-off-by: default avatarJia He <justin.he@arm.com>
Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
Expand speculative SSBS workaround")

CC: Mark Rutland <mark.rutland@arm.com>
CC: James More <james.morse@arm.com>
CC: Will Deacon <will@kernel.org>
CC: stable@vger.kernel.org # 6.6+
Signed-off-by: default avatarEaswar Hariharan <eahariha@linux.microsoft.com>
Link: https://lore.kernel.org/r/20241003225239.321774-1-eahariha@linux.microsoft.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarJia He <justin.he@arm.com>
parent 7c7228bc

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -296,3 +296,5 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #3324339        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/kernel/cpu_errata.c

+1 −0
Original line number Diff line number Diff line
@@ -550,6 +550,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = { 
	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),

	MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),