Commit 8febb297 authored by Eric Anholt's avatar Eric Anholt Committed by Keith Packard
Browse files

drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set(). 



Ironlake is where the PCH split started.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent db244b60

drivers/gpu/drm/i915/intel_display.c

+150 −209
Original line number Diff line number Diff line
@@ -4934,7 +4934,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	struct fdi_m_n m_n = {0};

	u32 reg, temp;

	u32 lvds_sync = 0;

	int target_clock;

	int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;



	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {

		if (encoder->base.crtc != crtc)
@@ -4976,8 +4976,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
			      refclk / 1000);

	} else if (!IS_GEN2(dev)) {

		refclk = 96000;

		if (HAS_PCH_SPLIT(dev) &&

		    (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))

		if (!has_edp_encoder ||

		    intel_encoder_is_pch_edp(&has_edp_encoder->base))

			refclk = 120000; /* 120Mhz refclk */

	} else {

		refclk = 48000;
@@ -5036,12 +5036,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	}



	/* FDI link */

	if (HAS_PCH_SPLIT(dev)) {

		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

		int lane = 0, link_bw, bpp;

	pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);

	lane = 0;

	/* CPU eDP doesn't require FDI link, so just set DP M/N

	   according to current link config */

		if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

	if (has_edp_encoder &&

	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

		target_clock = mode->clock;

		intel_edp_link_config(has_edp_encoder,

				      &lane, &link_bw);
@@ -5124,14 +5124,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	if (pixel_multiplier > 1)

		link_bw *= pixel_multiplier;

	ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);

	}



	/* Ironlake: try to setup display ref clock before DPLL

	 * enabling. This is only under driver's control after

	 * PCH B stepping, previous chipset stepping should be

	 * ignoring this setting.

	 */

	if (HAS_PCH_SPLIT(dev)) {

	temp = I915_READ(PCH_DREF_CONTROL);

	/* Always enable nonspread source */

	temp &= ~DREF_NONSPREAD_SOURCE_MASK;
@@ -5170,7 +5168,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		POSTING_READ(PCH_DREF_CONTROL);

		udelay(200);

	}

	}



	if (IS_PINEVIEW(dev)) {

		fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
@@ -5185,9 +5182,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	}



	/* Enable autotuning of the PLL clock (if permissible) */

	if (HAS_PCH_SPLIT(dev)) {

		int factor = 21;



	factor = 21;

	if (is_lvds) {

		if ((intel_panel_use_ssc(dev_priv) &&

		     dev_priv->lvds_ssc_freq == 100) ||
@@ -5198,11 +5193,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 


	if (clock.m1 < factor * clock.n)

		fp |= FP_CB_TUNE;

	}



	dpll = 0;

	if (!HAS_PCH_SPLIT(dev))

		dpll = DPLL_VGA_MODE_DIS;



	if (!IS_GEN2(dev)) {

		if (is_lvds)
@@ -5214,7 +5206,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
			if (pixel_multiplier > 1) {

				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))

					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;

				else if (HAS_PCH_SPLIT(dev))

				else

					dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;

			}

			dpll |= DPLL_DVO_HIGH_SPEED;
@@ -5228,7 +5220,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		else {

			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

			/* also FPA1 */

			if (HAS_PCH_SPLIT(dev))

			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

			if (IS_G4X(dev) && has_reduced_clock)

				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
@@ -5247,8 +5238,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

			break;

		}

		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))

			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

	} else {

		if (is_lvds) {

			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
@@ -5279,15 +5268,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	/* Set up the display plane register */

	dspcntr = DISPPLANE_GAMMA_ENABLE;



	/* Ironlake's plane is forced to pipe, bit 24 is to

	   enable color space conversion */

	if (!HAS_PCH_SPLIT(dev)) {

		if (pipe == 0)

			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;

		else

			dspcntr |= DISPPLANE_SEL_PIPE_B;

	}



	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {

		/* Enable pixel doubling when the dot clock is > 90% of the (display)

		 * core speed.
@@ -5302,20 +5282,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;

	}



	if (!HAS_PCH_SPLIT(dev))

		dpll |= DPLL_VCO_ENABLE;



	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');

	drm_mode_debug_printmodeline(mode);



	/* assign to Ironlake registers */

	if (HAS_PCH_SPLIT(dev)) {

	fp_reg = PCH_FP0(pipe);

	dpll_reg = PCH_DPLL(pipe);

	} else {

		fp_reg = FP0(pipe);

		dpll_reg = DPLL(pipe);

	}



	/* PCH eDP needs FDI, but CPU eDP does not */

	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
@@ -5354,8 +5326,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	 * things on.

	 */

	if (is_lvds) {

		reg = LVDS;

		if (HAS_PCH_SPLIT(dev))

		reg = PCH_LVDS;



		temp = I915_READ(reg);
@@ -5385,13 +5355,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		 * appropriately here, but we need to look more thoroughly into how

		 * panels behave in the two modes.

		 */

		/* set the dithering flag on non-PCH LVDS as needed */

		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {

			if (dev_priv->lvds_dither)

				temp |= LVDS_ENABLE_DITHER;

			else

				temp &= ~LVDS_ENABLE_DITHER;

		}

		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)

			lvds_sync |= LVDS_HSYNC_POLARITY;

		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -5412,18 +5375,16 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	}



	/* set the dithering flag and clear for anything other than a panel. */

	if (HAS_PCH_SPLIT(dev)) {

	pipeconf &= ~PIPECONF_DITHER_EN;

	pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;

	if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {

		pipeconf |= PIPECONF_DITHER_EN;

		pipeconf |= PIPECONF_DITHER_TYPE_ST1;

	}

	}



	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

		intel_dp_set_m_n(crtc, mode, adjusted_mode);

	} else if (HAS_PCH_SPLIT(dev)) {

	} else {

		/* For non-DP output, clear any trans DP clock recovery setting.*/

		I915_WRITE(TRANSDATA_M1(pipe), 0);

		I915_WRITE(TRANSDATA_N1(pipe), 0);
@@ -5431,24 +5392,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		I915_WRITE(TRANSDPLINK_N1(pipe), 0);

	}



	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

	if (!has_edp_encoder ||

	    intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

		I915_WRITE(dpll_reg, dpll);



		/* Wait for the clocks to stabilize. */

		POSTING_READ(dpll_reg);

		udelay(150);



		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {

			temp = 0;

			if (is_sdvo) {

				temp = intel_mode_get_pixel_multiplier(adjusted_mode);

				if (temp > 1)

					temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;

				else

					temp = 0;

			}

			I915_WRITE(DPLL_MD(pipe), temp);

		} else {

		/* The pixel multiplier can only be updated once the

		 * DPLL is enabled and the clocks are stable.

		 *
@@ -5456,7 +5407,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		 */

		I915_WRITE(dpll_reg, dpll);

	}

	}



	intel_crtc->lowfreq_avail = false;

	if (is_lvds && has_reduced_clock && i915_powersave) {
@@ -5506,33 +5456,24 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
		   (adjusted_mode->crtc_vsync_start - 1) |

		   ((adjusted_mode->crtc_vsync_end - 1) << 16));



	/* pipesrc and dspsize control the size that is scaled from,

	 * which should always be the user's requested size.

	/* pipesrc controls the size that is scaled from, which should

	 * always be the user's requested size.

	 */

	if (!HAS_PCH_SPLIT(dev)) {

		I915_WRITE(DSPSIZE(plane),

			   ((mode->vdisplay - 1) << 16) |

			   (mode->hdisplay - 1));

		I915_WRITE(DSPPOS(plane), 0);

	}

	I915_WRITE(PIPESRC(pipe),

		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));



	if (HAS_PCH_SPLIT(dev)) {

	I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);

	I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);

	I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);

	I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);



		if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

	if (has_edp_encoder &&

	    !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

		ironlake_set_pll_edp(crtc, adjusted_mode->clock);

	}

	}



	I915_WRITE(PIPECONF(pipe), pipeconf);

	POSTING_READ(PIPECONF(pipe));

	if (!HAS_PCH_SPLIT(dev))

		intel_enable_pipe(dev_priv, pipe, false);



	intel_wait_for_vblank(dev, pipe);