Commit 8fe6f7e1 authored Mar 06, 2023 by Anup Patel Committed by Anup Patel Apr 21, 2023

RISC-V: Detect AIA CSRs from ISA string



We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs)
and Ssaia (S-mode AIA CSRs).

We extend the ISA string parsing to detect Smaia and Ssaia extensions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

parent d6f5f6e9

arch/riscv/include/asm/hwcap.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,8 @@
		#define RISCV_ISA_EXT_ZBB 30
		#define RISCV_ISA_EXT_ZICBOM 31
		#define RISCV_ISA_EXT_ZIHINTPAUSE 32
		#define RISCV_ISA_EXT_SMAIA 33
		#define RISCV_ISA_EXT_SSAIA 34

		#define RISCV_ISA_EXT_MAX 64
		#define RISCV_ISA_EXT_NAME_LEN_MAX 32

arch/riscv/kernel/cpu.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -188,6 +188,8 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
		__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
		__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
		__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
		__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
		__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
		__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
		__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
		__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),

arch/riscv/kernel/cpufeature.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -221,6 +221,8 @@ void __init riscv_fill_hwcap(void)
		}
		} else {
		/* sorted alphabetically */
		SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
		SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
		SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
		SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
		SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);