Commit 8fdb61f1 authored by jason-jh.lin's avatar jason-jh.lin Committed by Matthias Brugger
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soc: mediatek: add mtk-mutex support for mt8195 vdosys0 



Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: default avatarjason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: default avatarFei Shao <fshao@chromium.org>
Reviewed-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220419094143.9561-3-jason-jh.lin@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent b804923b

drivers/soc/mediatek/mtk-mutex.c

+84 −3
Original line number Diff line number Diff line
@@ -17,6 +17,9 @@ 
#define MT8183_MUTEX0_MOD0			0x30

#define MT8183_MUTEX0_SOF0			0x2c



#define MT8195_DISP_MUTEX0_MOD0			0x30

#define MT8195_DISP_MUTEX0_SOF			0x2c



#define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))

#define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))

#define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@ 
#define MT8173_MUTEX_MOD_DISP_PWM1		24

#define MT8173_MUTEX_MOD_DISP_OD		25



#define MT8195_MUTEX_MOD_DISP_OVL0		0

#define MT8195_MUTEX_MOD_DISP_WDMA0		1

#define MT8195_MUTEX_MOD_DISP_RDMA0		2

#define MT8195_MUTEX_MOD_DISP_COLOR0		3

#define MT8195_MUTEX_MOD_DISP_CCORR0		4

#define MT8195_MUTEX_MOD_DISP_AAL0		5

#define MT8195_MUTEX_MOD_DISP_GAMMA0		6

#define MT8195_MUTEX_MOD_DISP_DITHER0		7

#define MT8195_MUTEX_MOD_DISP_DSI0		8

#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9

#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20

#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21

#define MT8195_MUTEX_MOD_DISP_PWM0		27



#define MT2712_MUTEX_MOD_DISP_PWM2		10

#define MT2712_MUTEX_MOD_DISP_OVL0		11

#define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -132,9 +149,21 @@ 
#define MT8167_MUTEX_SOF_DPI1			3

#define MT8183_MUTEX_SOF_DSI0			1

#define MT8183_MUTEX_SOF_DPI0			2

#define MT8195_MUTEX_SOF_DSI0			1

#define MT8195_MUTEX_SOF_DSI1			2

#define MT8195_MUTEX_SOF_DP_INTF0		3

#define MT8195_MUTEX_SOF_DP_INTF1		4

#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */

#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */



#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)

#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)

#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)

#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)

#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)

#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)

#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)

#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)



struct mtk_mutex {

	int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id { 
	MUTEX_SOF_DPI1,

	MUTEX_SOF_DSI2,

	MUTEX_SOF_DSI3,

	MUTEX_SOF_DP_INTF0,

	MUTEX_SOF_DP_INTF1,

	DDP_MUTEX_SOF_MAX,

};



struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { 
	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,

};



static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {

static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {

	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,

	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,

	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,

	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,

	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,

	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,

	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,

	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,

	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,

	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,

	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,

	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,

	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,

};



static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {

	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,

	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,

	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 
	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,

};



static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {

static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {

	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,

	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,

	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 
};



/* Add EOF setting so overlay hardware can receive frame done irq */

static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {

static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {

	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,

	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,

	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { 
	[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,

};



/*

 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should

 * select the EOF source and configure the EOF plus timing from the

 * module that provides the timing signal.

 * So that MUTEX can not only send a STREAM_DONE event to GCE

 * but also detect the error at end of frame(EAEOF) when EOF signal

 * arrives.

 */

static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {

	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,

	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,

	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,

	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,

	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,

	[MUTEX_SOF_DP_INTF0] =

		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,

	[MUTEX_SOF_DP_INTF1] =

		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,

};



static const struct mtk_mutex_data mt2701_mutex_driver_data = {

	.mutex_mod = mt2701_mutex_mod,

	.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = { 
	.mutex_sof_reg = MT8183_MUTEX0_SOF0,

};



static const struct mtk_mutex_data mt8195_mutex_driver_data = {

	.mutex_mod = mt8195_mutex_mod,

	.mutex_sof = mt8195_mutex_sof,

	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,

	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,

};



struct mtk_mutex *mtk_mutex_get(struct device *dev)

{

	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, 
	case DDP_COMPONENT_DPI1:

		sof_id = MUTEX_SOF_DPI1;

		break;

	case DDP_COMPONENT_DP_INTF0:

		sof_id = MUTEX_SOF_DP_INTF0;

		break;

	default:

		if (mtx->data->mutex_mod[id] < 32) {

			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, 
	case DDP_COMPONENT_DSI3:

	case DDP_COMPONENT_DPI0:

	case DDP_COMPONENT_DPI1:

	case DDP_COMPONENT_DP_INTF0:

		writel_relaxed(MUTEX_SOF_SINGLE_MODE,

			       mtx->regs +

			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { 
	  .data = &mt8186_mutex_driver_data},

	{ .compatible = "mediatek,mt8192-disp-mutex",

	  .data = &mt8192_mutex_driver_data},

	{ .compatible = "mediatek,mt8195-disp-mutex",

	  .data = &mt8195_mutex_driver_data},

	{},

};

MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);