Commit 8f6707d0 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Vinod Koul
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dmaengine: ioat: use PCI core macros for PCIe Capability



The PCIe Capability is defined by the PCIe spec, so use the PCI_EXP_DEVCTL
macros defined by the PCI core instead of defining copies in IOAT.  This
makes it easier to find all uses of the PCIe Device Control register.  No
functional change intended.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20230307214615.887354-1-helgaas@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 3765af04
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+3 −3
Original line number Diff line number Diff line
@@ -1191,13 +1191,13 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
		ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);

	/* disable relaxed ordering */
	err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
	err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16);
	if (err)
		return pcibios_err_to_errno(err);

	/* clear relaxed ordering enable */
	val16 &= ~IOAT_DEVCTRL_ROE;
	err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
	val16 &= ~PCI_EXP_DEVCTL_RELAX_EN;
	err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16);
	if (err)
		return pcibios_err_to_errno(err);

+0 −7
Original line number Diff line number Diff line
@@ -14,13 +14,6 @@
#define IOAT_PCI_CHANERR_INT_OFFSET		0x180
#define IOAT_PCI_CHANERRMASK_INT_OFFSET		0x184

/* PCIe config registers */

/* EXPCAPID + N */
#define IOAT_DEVCTRL_OFFSET			0x8
/* relaxed ordering enable */
#define IOAT_DEVCTRL_ROE			0x10

/* MMIO Device Registers */
#define IOAT_CHANCNT_OFFSET			0x00	/*  8-bit */