Commit 8f0d60fe authored by Jinzhou Su's avatar Jinzhou Su Committed by Alex Deucher
Browse files

drm/amdgpu: modify GCR_GENERAL_CNTL for Vangogh 



GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and
gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh.

Signed-off-by: default avatarJinzhou Su <Jinzhou.Su@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 51e87da7

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −1
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ 
#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1

#define mmSPI_CONFIG_CNTL_Vangogh                0x2440

#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1

#define mmGCR_GENERAL_CNTL_Vangogh               0x1580

#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0



#define mmCP_HYP_PFP_UCODE_ADDR			0x5814

#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
@@ -3244,7 +3246,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),