Commit 8f0ae6bc authored by Devi Priya's avatar Devi Priya Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: ipq9574: Add cpufreq support 



Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: default avatarPraveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: default avatarPraveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: default avatarDevi Priya <quic_devipriy@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230517172527.1968-4-quic_devipriy@quicinc.com
parent 56ba2b3a

arch/arm64/boot/dts/qcom/ipq9574.dtsi

+59 −1
Original line number Diff line number Diff line
@@ -6,8 +6,9 @@ 
 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,apss-ipq.h>

#include <dt-bindings/clock/qcom,ipq9574-gcc.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/qcom,ipq9574-gcc.h>



/ {
@@ -37,6 +38,10 @@ 
			reg = <0x0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq9574_s1>;

		};



		CPU1: cpu@1 {
@@ -45,6 +50,10 @@ 
			reg = <0x1>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq9574_s1>;

		};



		CPU2: cpu@2 {
@@ -53,6 +62,10 @@ 
			reg = <0x2>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq9574_s1>;

		};



		CPU3: cpu@3 {
@@ -61,6 +74,10 @@ 
			reg = <0x3>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu_opp_table>;

			cpu-supply = <&ipq9574_s1>;

		};



		L2_0: l2-cache {
@@ -82,6 +99,47 @@ 
		reg = <0x0 0x40000000 0x0 0x0>;

	};



	cpu_opp_table: opp-table-cpu {

		compatible = "operating-points-v2";

		opp-shared;



		opp-936000000 {

			opp-hz = /bits/ 64 <936000000>;

			opp-microvolt = <725000>;

			clock-latency-ns = <200000>;

		};



		opp-1104000000 {

			opp-hz = /bits/ 64 <1104000000>;

			opp-microvolt = <787500>;

			clock-latency-ns = <200000>;

		};



		opp-1416000000 {

			opp-hz = /bits/ 64 <1416000000>;

			opp-microvolt = <862500>;

			clock-latency-ns = <200000>;

		};



		opp-1488000000 {

			opp-hz = /bits/ 64 <1488000000>;

			opp-microvolt = <925000>;

			clock-latency-ns = <200000>;

		};



		opp-1800000000 {

			opp-hz = /bits/ 64 <1800000000>;

			opp-microvolt = <987500>;

			clock-latency-ns = <200000>;

		};



		opp-2208000000 {

			opp-hz = /bits/ 64 <2208000000>;

			opp-microvolt = <1062500>;

			clock-latency-ns = <200000>;

		};

	};



	pmu {

		compatible = "arm,cortex-a73-pmu";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;