Commit 8f058a6e authored by Arınç ÜNAL's avatar Arınç ÜNAL Committed by Jakub Kicinski
Browse files

net: dsa: mt7530: move enabling disabling core clock to mt7530_pll_setup() 

Split the code that enables and disables TRGMII clocks and core clock.
Move enabling and disabling core clock to mt7530_pll_setup() as it's
supposed to be run there.

Add 20 ms delay before enabling the core clock as seen on the U-Boot
MediaTek ethernet driver.

Change the comment for enabling and disabling TRGMII clocks as the code
seems to affect both TXC and RXC.

Tested rgmii and trgmii modes of port 6 and rgmii mode of port 5 on MCM
MT7530 on MT7621AT Unielec U7621-06 and standalone MT7530 on MT7623NI
Bananapi BPI-R2.

Fixes: b8f126a8 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
Link: https://source.denx.de/u-boot/u-boot/-/blob/29a48bf9ccba45a5e560bb564bbe76e42629325f/drivers/net/mtk_eth.c#L589


Tested-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/r/20230320190520.124513-1-arinc.unal@arinc9.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 8eac0095

drivers/net/dsa/mt7530.c

+12 −6
Original line number Diff line number Diff line
@@ -396,6 +396,9 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 
/* Set up switch core clock for MT7530 */

static void mt7530_pll_setup(struct mt7530_priv *priv)

{

	/* Disable core clock */

	core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);



	/* Disable PLL */

	core_write(priv, CORE_GSWPLL_GRP1, 0);
@@ -409,6 +412,11 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) 
		   RG_GSWPLL_EN_PRE |

		   RG_GSWPLL_POSDIV_200M(2) |

		   RG_GSWPLL_FBKDIV_200M(32));



	udelay(20);



	/* Enable core clock */

	core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);

}



/* Setup TX circuit including relevant PAD and driving */
@@ -466,9 +474,8 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 
			mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),

				     TD_DM_DRVP(8) | TD_DM_DRVN(8));



		/* Disable MT7530 core and TRGMII Tx clocks */

		core_clear(priv, CORE_TRGMII_GSW_CLK_CG,

			   REG_GSWCK_EN | REG_TRGMIICK_EN);

		/* Disable the MT7530 TRGMII clocks */

		core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);



		/* Setup the MT7530 TRGMII Tx Clock */

		core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
@@ -485,9 +492,8 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 
			   RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |

			   RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);



		/* Enable MT7530 core and TRGMII Tx clocks */

		core_set(priv, CORE_TRGMII_GSW_CLK_CG,

			 REG_GSWCK_EN | REG_TRGMIICK_EN);

		/* Enable the MT7530 TRGMII clocks */

		core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);

	} else {

		for (i = 0 ; i < NUM_TRGMII_CTRL; i++)

			mt7530_rmw(priv, MT7530_TRGMII_RD(i),