Commit 8ee0fea4 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: fix dml prefetch validation 



Incorrect variable used, missing initialization during validation.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5cf0a610

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

+1 −0
Original line number Diff line number Diff line
@@ -3437,6 +3437,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
			mode_lib->vba.DCCEnabledInAnyPlane = true;

		}

	}

	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;

	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {

		locals->FabricAndDRAMBandwidthPerState[i] = dml_min(

				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

+1 −0
Original line number Diff line number Diff line
@@ -3544,6 +3544,7 @@ void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode 
			mode_lib->vba.DCCEnabledInAnyPlane = true;

		}

	}

	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;

	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {

		locals->FabricAndDRAMBandwidthPerState[i] = dml_min(

				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels