crypto: octeontx2 - add support to process the crypto request (8ec8015a) · Commits · EulixOS / Software / Kernel

drivers/crypto/marvell/octeontx2/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -4,6 +4,6 @@ obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o octeontx2-cptvf.o
		octeontx2-cpt-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \
		otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o
		octeontx2-cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \
		otx2_cpt_mbox_common.o
		otx2_cpt_mbox_common.o otx2_cptvf_reqmgr.o

		ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+17 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,9 @@
		#define OTX2_CPT_MAX_VFS_NUM 128
		#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
		(((blk) << 20) \| ((slot) << 12) \| (offs))
		#define OTX2_CPT_RVU_PFFUNC(pf, func) \
		((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) \| \
		(((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))

		#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
		#define OTX2_CPT_NAME_LENGTH 64
		@@ -34,6 +37,7 @@ enum otx2_cpt_eng_type {
		/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
		#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
		#define MBOX_MSG_GET_CAPS 0xBFD
		#define MBOX_MSG_GET_KVF_LIMITS 0xBFC

		/*
		* Message request and response to get engine group number
		@@ -51,6 +55,19 @@ struct otx2_cpt_egrp_num_rsp {
		u8 eng_grp_num;
		};

		/*
		* Message request and response to get kernel crypto limits
		* This messages are only used between CPT PF <-> CPT VF
		*/
		struct otx2_cpt_kvf_limits_msg {
		struct mbox_msghdr hdr;
		};

		struct otx2_cpt_kvf_limits_rsp {
		struct mbox_msghdr hdr;
		u8 kvf_limits;
		};

		/* CPT HW capabilities */
		union otx2_cpt_eng_caps {
		u64 u;

drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h

+145 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,22 @@
		/* Completion code size and initial value */
		#define OTX2_CPT_COMPLETION_CODE_SIZE 8
		#define OTX2_CPT_COMPLETION_CODE_INIT OTX2_CPT_COMP_E_NOTDONE
		/*
		* Maximum total number of SG buffers is 100, we divide it equally
		* between input and output
		*/
		#define OTX2_CPT_MAX_SG_IN_CNT 50
		#define OTX2_CPT_MAX_SG_OUT_CNT 50

		/* DMA mode direct or SG */
		#define OTX2_CPT_DMA_MODE_DIRECT 0
		#define OTX2_CPT_DMA_MODE_SG 1

		/* Context source CPTR or DPTR */
		#define OTX2_CPT_FROM_CPTR 0
		#define OTX2_CPT_FROM_DPTR 1

		#define OTX2_CPT_MAX_REQ_SIZE 65535

		union otx2_cpt_opcode {
		u16 flags;
		@@ -19,6 +35,13 @@ union otx2_cpt_opcode {
		} s;
		};

		struct otx2_cptvf_request {
		u32 param1;
		u32 param2;
		u16 dlen;
		union otx2_cpt_opcode opcode;
		};

		/*
		* CPT_INST_S software command definitions
		* Words EI (0-3)
		@@ -48,4 +71,126 @@ struct otx2_cpt_iq_command {
		union otx2_cpt_iq_cmd_word3 cptr;
		};

		struct otx2_cpt_pending_entry {
		void completion_addr; / Completion address */
		void *info;
		/* Kernel async request callback */
		void (callback)(int status, void arg1, void *arg2);
		struct crypto_async_request areq; / Async request callback arg */
		u8 resume_sender; /* Notify sender to resume sending requests */
		u8 busy; /* Entry status (free/busy) */
		};

		struct otx2_cpt_pending_queue {
		struct otx2_cpt_pending_entry head; / Head of the queue */
		u32 front; /* Process work from here */
		u32 rear; /* Append new work here */
		u32 pending_count; /* Pending requests count */
		u32 qlen; /* Queue length */
		spinlock_t lock; /* Queue lock */
		};

		struct otx2_cpt_buf_ptr {
		u8 *vptr;
		dma_addr_t dma_addr;
		u16 size;
		};

		union otx2_cpt_ctrl_info {
		u32 flags;
		struct {
		#if defined(__BIG_ENDIAN_BITFIELD)
		u32 reserved_6_31:26;
		u32 grp:3; /* Group bits */
		u32 dma_mode:2; /* DMA mode */
		u32 se_req:1; /* To SE core */
		#else
		u32 se_req:1; /* To SE core */
		u32 dma_mode:2; /* DMA mode */
		u32 grp:3; /* Group bits */
		u32 reserved_6_31:26;
		#endif
		} s;
		};

		struct otx2_cpt_req_info {
		/* Kernel async request callback */
		void (callback)(int status, void arg1, void *arg2);
		struct crypto_async_request areq; / Async request callback arg */
		struct otx2_cptvf_request req;/* Request information (core specific) */
		union otx2_cpt_ctrl_info ctrl;/* User control information */
		struct otx2_cpt_buf_ptr in[OTX2_CPT_MAX_SG_IN_CNT];
		struct otx2_cpt_buf_ptr out[OTX2_CPT_MAX_SG_OUT_CNT];
		u8 iv_out; / IV to send back */
		u16 rlen; /* Output length */
		u8 in_cnt; /* Number of input buffers */
		u8 out_cnt; /* Number of output buffers */
		u8 req_type; /* Type of request */
		u8 is_enc; /* Is a request an encryption request */
		u8 is_trunc_hmac;/* Is truncated hmac used */
		};

		struct otx2_cpt_inst_info {
		struct otx2_cpt_pending_entry *pentry;
		struct otx2_cpt_req_info *req;
		struct pci_dev *pdev;
		void *completion_addr;
		u8 *out_buffer;
		u8 *in_buffer;
		dma_addr_t dptr_baddr;
		dma_addr_t rptr_baddr;
		dma_addr_t comp_baddr;
		unsigned long time_in;
		u32 dlen;
		u32 dma_len;
		u8 extra_time;
		};

		struct otx2_cpt_sglist_component {
		__be16 len0;
		__be16 len1;
		__be16 len2;
		__be16 len3;
		__be64 ptr0;
		__be64 ptr1;
		__be64 ptr2;
		__be64 ptr3;
		};

		static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,
		struct otx2_cpt_inst_info *info)
		{
		struct otx2_cpt_req_info *req;
		int i;

		if (info->dptr_baddr)
		dma_unmap_single(&pdev->dev, info->dptr_baddr,
		info->dma_len, DMA_BIDIRECTIONAL);

		if (info->req) {
		req = info->req;
		for (i = 0; i < req->out_cnt; i++) {
		if (req->out[i].dma_addr)
		dma_unmap_single(&pdev->dev,
		req->out[i].dma_addr,
		req->out[i].size,
		DMA_BIDIRECTIONAL);
		}

		for (i = 0; i < req->in_cnt; i++) {
		if (req->in[i].dma_addr)
		dma_unmap_single(&pdev->dev,
		req->in[i].dma_addr,
		req->in[i].size,
		DMA_BIDIRECTIONAL);
		}
		}
		kfree(info);
		}

		struct otx2_cptlf_wqe;
		int otx2_cpt_do_request(struct pci_dev pdev, struct otx2_cpt_req_info req,
		int cpu_num);
		void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe);

		#endif /* __OTX2_CPT_REQMGR_H */

drivers/crypto/marvell/octeontx2/otx2_cptlf.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -80,6 +80,7 @@ struct otx2_cptlf_info {
		u8 slot; /* Slot number of this LF */

		struct otx2_cpt_inst_queue iqueue;/* Instruction queue */
		struct otx2_cpt_pending_queue pqueue; /* Pending queue */
		struct otx2_cptlf_wqe wqe; / Tasklet work info */
		};

		@@ -91,6 +92,8 @@ struct otx2_cptlfs_info {
		struct otx2_mbox *mbox;
		u8 are_lfs_attached; /* Whether CPT LFs are attached */
		u8 lfs_num; /* Number of CPT LFs */
		u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */
		u8 kvf_limits; /* Kernel crypto limits */
		atomic_t state; /* LF's state. started/reset */
		};

		@@ -334,6 +337,11 @@ static inline void otx2_cpt_send_cmd(union otx2_cpt_inst_s *cptinst,
		} while (!ret);
		}

		static inline bool otx2_cptlf_started(struct otx2_cptlfs_info *lfs)
		{
		return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;
		}

		int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_msk, int pri,
		int lfs_num);
		void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs);

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,7 @@ struct otx2_cptpf_dev {
		u8 pf_id; /* RVU PF number */
		u8 max_vfs; /* Maximum number of VFs supported by CPT */
		u8 enabled_vfs; /* Number of enabled VFs */
		u8 kvf_limits; /* Kernel crypto limits */
		};

		irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);