Commit 8ea673a8 authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
Browse files

PCI: pci-bridge-emul: Add definitions for missing capabilities registers 

pci-bridge-emul driver already allocates buffer for capabilities up to the
PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
registers. Add these missing definitions.

Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org


Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 9319230a

drivers/pci/pci-bridge-emul.c

+43 −0
Original line number Diff line number Diff line
@@ -251,6 +251,49 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = 
		.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,

		.w1c = PCI_EXP_RTSTA_PME,

	},



	[PCI_EXP_DEVCAP2 / 4] = {

		/*

		 * Device capabilities 2 register has reserved bits [30:27].

		 * Also bits [26:24] are reserved for non-upstream ports.

		 */

		.ro = BIT(31) | GENMASK(23, 0),

	},



	[PCI_EXP_DEVCTL2 / 4] = {

		/*

		 * Device control 2 register is RW. Bit 11 is reserved for

		 * non-upstream ports.

		 *

		 * Device status 2 register is reserved.

		 */

		.rw = GENMASK(15, 12) | GENMASK(10, 0),

	},



	[PCI_EXP_LNKCAP2 / 4] = {

		/* Link capabilities 2 register has reserved bits [30:25] and 0. */

		.ro = BIT(31) | GENMASK(24, 1),

	},



	[PCI_EXP_LNKCTL2 / 4] = {

		/*

		 * Link control 2 register is RW.

		 *

		 * Link status 2 register has bits 5, 15 W1C;

		 * bits 10, 11 reserved and others are RO.

		 */

		.rw = GENMASK(15, 0),

		.w1c = (BIT(15) | BIT(5)) << 16,

		.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,

	},



	[PCI_EXP_SLTCAP2 / 4] = {

		/* Slot capabilities 2 register is reserved. */

	},



	[PCI_EXP_SLTCTL2 / 4] = {

		/* Both Slot control 2 and Slot status 2 registers are reserved. */

	},

};



/*