Commit 8ea432b8 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: drop duplicated intf/wb indices from encoder structs 



Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.

Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Patchwork: https://patchwork.freedesktop.org/patch/540635/
Link: https://lore.kernel.org/r/20230601172236.564445-4-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 7731ee3b

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+30 −42
Original line number Diff line number Diff line
@@ -339,7 +339,8 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 
	DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",

			DRMID(phys_enc->parent),

			dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),

			phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,

			phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,

			phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,

			phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);



	dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
@@ -1419,7 +1420,8 @@ void dpu_encoder_frame_done_callback( 
			 */

			trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,

					dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),

					ready_phys->intf_idx, ready_phys->wb_idx);

					ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,

					ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);

			return;

		}
@@ -1499,7 +1501,8 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc, 


	trace_dpu_enc_trigger_flush(DRMID(drm_enc),

			dpu_encoder_helper_get_intf_type(phys->intf_mode),

			phys->intf_idx, phys->wb_idx,

			phys->hw_intf ? phys->hw_intf->idx : -1,

			phys->hw_wb ? phys->hw_wb->idx : -1,

			pending_kickoff_cnt, ctl->idx,

			extra_flush_bits, ret);

}
@@ -2155,7 +2158,8 @@ static int _dpu_encoder_status_show(struct seq_file *s, void *data) 
		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];



		seq_printf(s, "intf:%d  wb:%d  vsync:%8d     underrun:%8d    ",

				phys->intf_idx - INTF_0, phys->wb_idx - WB_0,

				phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,

				phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,

				atomic_read(&phys->vsync_cnt),

				atomic_read(&phys->underrun_cnt));
@@ -2319,6 +2323,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 
		 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right

		 */

		u32 controller_id = disp_info->h_tile_instance[i];

		enum dpu_intf intf_idx;

		enum dpu_wb wb_idx;



		if (disp_info->num_of_h_tiles > 1) {

			if (i == 0)
@@ -2332,57 +2338,39 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, 
		DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",

				i, controller_id, phys_params.split_role);



		phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,

		intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,

							    disp_info->intf_type,

							    controller_id);



		phys_params.wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,

		wb_idx = dpu_encoder_get_wb(dpu_kms->catalog,

				disp_info->intf_type, controller_id);

		/*

		 * The phys_params might represent either an INTF or a WB unit, but not

		 * both of them at the same time.

		 */

		if ((phys_params.intf_idx == INTF_MAX) &&

				(phys_params.wb_idx == WB_MAX)) {

			DPU_ERROR_ENC(dpu_enc, "could not get intf or wb: type %d, id %d\n",

						  disp_info->intf_type, controller_id);

			ret = -EINVAL;

		}



		if ((phys_params.intf_idx != INTF_MAX) &&

				(phys_params.wb_idx != WB_MAX)) {

			DPU_ERROR_ENC(dpu_enc, "both intf and wb present: type %d, id %d\n",

						  disp_info->intf_type, controller_id);

			ret = -EINVAL;

		}

		if (intf_idx >= INTF_0 && intf_idx < INTF_MAX)

			phys_params.hw_intf = dpu_rm_get_intf(&dpu_kms->rm, intf_idx);



		if (!ret) {

			ret = dpu_encoder_virt_add_phys_encs(disp_info,

					dpu_enc, &phys_params);

			if (ret)

				DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");

		}

	}

		if (wb_idx >= WB_0 && wb_idx < WB_MAX)

			phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, wb_idx);



	for (i = 0; i < dpu_enc->num_phys_encs; i++) {

		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];



		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)

			phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);



		if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)

			phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);



		if (!phys->hw_intf && !phys->hw_wb) {

		if (!phys_params.hw_intf && !phys_params.hw_wb) {

			DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);

			ret = -EINVAL;

			break;

		}



		if (phys->hw_intf && phys->hw_wb) {

		if (phys_params.hw_intf && phys_params.hw_wb) {

			DPU_ERROR_ENC(dpu_enc,

					"invalid phys both intf and wb block at idx: %d\n", i);

			ret = -EINVAL;

			break;

		}



		ret = dpu_encoder_virt_add_phys_encs(disp_info,

				dpu_enc, &phys_params);

		if (ret) {

			DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");

			break;

		}



	}



	mutex_unlock(&dpu_enc->enc_lock);
@@ -2574,8 +2562,8 @@ void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc, 
	int i;



	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;

	phys_enc->intf_idx = p->intf_idx;

	phys_enc->wb_idx = p->wb_idx;

	phys_enc->hw_intf = p->hw_intf;

	phys_enc->hw_wb = p->hw_wb;

	phys_enc->parent = p->parent;

	phys_enc->dpu_kms = p->dpu_kms;

	phys_enc->split_role = p->split_role;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+4 −8
Original line number Diff line number Diff line
@@ -161,8 +161,6 @@ enum dpu_intr_idx { 
 * @enabled:		Whether the encoder has enabled and running a mode

 * @split_role:		Role to play in a split-panel configuration

 * @intf_mode:		Interface mode

 * @intf_idx:		Interface index on dpu hardware

 * @wb_idx:			Writeback index on dpu hardware

 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes

 * @enable_state:	Enable state tracking

 * @vblank_refcount:	Reference count of vblank request
@@ -190,8 +188,6 @@ struct dpu_encoder_phys { 
	struct drm_display_mode cached_mode;

	enum dpu_enc_split_role split_role;

	enum dpu_intf_mode intf_mode;

	enum dpu_intf intf_idx;

	enum dpu_wb wb_idx;

	spinlock_t *enc_spinlock;

	enum dpu_enc_enable_state enable_state;

	atomic_t vblank_refcount;
@@ -258,16 +254,16 @@ struct dpu_encoder_phys_cmd { 
 * @parent:		Pointer to the containing virtual encoder

 * @parent_ops:		Callbacks exposed by the parent to the phys_enc

 * @split_role:		Role to play in a split-panel configuration

 * @intf_idx:		Interface index this phys_enc will control

 * @wb_idx:			Writeback index this phys_enc will control

 * @hw_intf:		Hardware interface to the intf registers

 * @hw_wb:		Hardware interface to the wb registers

 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes

 */

struct dpu_enc_phys_init_params {

	struct dpu_kms *dpu_kms;

	struct drm_encoder *parent;

	enum dpu_enc_split_role split_role;

	enum dpu_intf intf_idx;

	enum dpu_wb wb_idx;

	struct dpu_hw_intf *hw_intf;

	struct dpu_hw_wb *hw_wb;

	spinlock_t *enc_spinlock;

};

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

+9 −9
Original line number Diff line number Diff line
@@ -16,12 +16,12 @@ 
#define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \

		(e) && (e)->base.parent ? \

		(e)->base.parent->base.id : -1, \

		(e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)

		(e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)



#define DPU_ERROR_CMDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \

		(e) && (e)->base.parent ? \

		(e)->base.parent->base.id : -1, \

		(e) ? (e)->base.intf_idx - INTF_0 : -1, ##__VA_ARGS__)

		(e) ? (e)->base.hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)



#define to_dpu_encoder_phys_cmd(x) \

	container_of(x, struct dpu_encoder_phys_cmd, base)
@@ -55,7 +55,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( 
	if (!ctl->ops.setup_intf_cfg)

		return;



	intf_cfg.intf = phys_enc->intf_idx;

	intf_cfg.intf = phys_enc->hw_intf->idx;

	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;

	intf_cfg.stream_sel = cmd_enc->stream_sel;

	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
@@ -440,7 +440,7 @@ static void dpu_encoder_phys_cmd_enable_helper( 
		return;

	}



	dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);

	dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);



	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
@@ -448,7 +448,7 @@ static void dpu_encoder_phys_cmd_enable_helper( 
		return;



	ctl = phys_enc->hw_ctl;

	ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);

	ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);

}



static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
@@ -557,7 +557,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) 
				phys_enc->hw_pp->idx);



		ctl = phys_enc->hw_ctl;

		ctl->ops.update_pending_flush_intf(ctl, phys_enc->intf_idx);

		ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);

	}



	phys_enc->enable_state = DPU_ENC_DISABLED;
@@ -667,7 +667,7 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( 
	if (rc) {

		DRM_ERROR("failed wait_for_idle: id:%u ret:%d intf:%d\n",

			  DRMID(phys_enc->parent), rc,

			  phys_enc->intf_idx - INTF_0);

			  phys_enc->hw_intf->idx - INTF_0);

	}



	return rc;
@@ -758,7 +758,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 
	struct dpu_encoder_phys_cmd *cmd_enc = NULL;

	int ret = 0;



	DPU_DEBUG("intf %d\n", p->intf_idx - INTF_0);

	DPU_DEBUG("intf\n");



	cmd_enc = kzalloc(sizeof(*cmd_enc), GFP_KERNEL);

	if (!cmd_enc) {
@@ -775,7 +775,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 
	cmd_enc->stream_sel = 0;



	phys_enc->has_intf_te = test_bit(DPU_INTF_TE,

			&phys_enc->dpu_kms->catalog->intf[p->intf_idx - INTF_0].features);

					 &phys_enc->hw_intf->cap->features);



	atomic_set(&cmd_enc->pending_vblank_cnt, 0);

	init_waitqueue_head(&cmd_enc->pending_vblank_wq);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+1 −1
Original line number Diff line number Diff line
@@ -718,7 +718,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 
	dpu_encoder_phys_vid_init_ops(&phys_enc->ops);

	phys_enc->intf_mode = INTF_MODE_VIDEO;



	DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx);

	DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx);



	return phys_enc;

}

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

+3 −5
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ static int dpu_encoder_phys_wb_atomic_check( 
	const struct drm_display_mode *mode = &crtc_state->mode;



	DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",

			phys_enc->wb_idx, mode->name, mode->hdisplay, mode->vdisplay);

			phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);



	if (!conn_state || !conn_state->connector) {

		DPU_ERROR("invalid connector state\n");
@@ -561,7 +561,7 @@ static void dpu_encoder_phys_wb_destroy(struct dpu_encoder_phys *phys_enc) 
	if (!phys_enc)

		return;



	DPU_DEBUG("[wb:%d]\n", phys_enc->wb_idx - WB_0);

	DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);



	kfree(phys_enc);

}
@@ -712,9 +712,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init( 


	wb_enc->wb_done_timeout_cnt = 0;





	DPU_DEBUG("Created dpu_encoder_phys for wb %d\n",

			phys_enc->wb_idx);

	DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);



	return phys_enc;