Unverified Commit 8e9b1c95 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Palmer Dabbelt
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riscv: dts: sifive: Group tuples in register properties 



To improve human readability and enable automatic validation, the tuples
in "reg" properties containing register blocks should be grouped using
angle brackets.

Signed-off-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent cc79be0e

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -196,8 +196,8 @@ 
		};

		qspi0: spi@10040000 {

			compatible = "sifive,fu540-c000-spi", "sifive,spi0";

			reg = <0x0 0x10040000 0x0 0x1000

			       0x0 0x20000000 0x0 0x10000000>;

			reg = <0x0 0x10040000 0x0 0x1000>,

			      <0x0 0x20000000 0x0 0x10000000>;

			interrupt-parent = <&plic0>;

			interrupts = <51>;

			clocks = <&prci PRCI_CLK_TLCLK>;
@@ -207,8 +207,8 @@ 
		};

		qspi1: spi@10041000 {

			compatible = "sifive,fu540-c000-spi", "sifive,spi0";

			reg = <0x0 0x10041000 0x0 0x1000

			       0x0 0x30000000 0x0 0x10000000>;

			reg = <0x0 0x10041000 0x0 0x1000>,

			      <0x0 0x30000000 0x0 0x10000000>;

			interrupt-parent = <&plic0>;

			interrupts = <52>;

			clocks = <&prci PRCI_CLK_TLCLK>;
@@ -230,8 +230,8 @@ 
			compatible = "sifive,fu540-c000-gem";

			interrupt-parent = <&plic0>;

			interrupts = <53>;

			reg = <0x0 0x10090000 0x0 0x2000

			       0x0 0x100a0000 0x0 0x1000>;

			reg = <0x0 0x10090000 0x0 0x2000>,

			      <0x0 0x100a0000 0x0 0x1000>;

			local-mac-address = [00 00 00 00 00 00];

			clock-names = "pclk", "hclk";

			clocks = <&prci PRCI_CLK_GEMGXLPLL>,