Commit 8e8fc62d authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'txgbe-link-modes' 



Jiawen Wu says:

====================
support more link mode for TXGBE

There are three new interface mode support for Wangxun 10Gb NICs:
1000BASE-X, SGMII and XAUI.

Specific configurations are added to XPCS. And external PHY attaching
is added for copper NICs.

v2 -> v3:
- add device identifier read
- restrict pcs soft reset
- add firmware version warning

v1 -> v2:
- use the string "txgbe_pcs_mdio_bus" directly
- use dev_err() instead of pr_err()
- add device quirk flag
- add more macro definitions to explain PMA registers
- move txgbe_enable_sec_tx_path() to mac_finish()
- implement phylink for copper NICs
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1355fe13 ad63f7aa

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -22925,6 +22925,7 @@ S: Maintained 
W:	https://www.net-swift.com

F:	Documentation/networking/device_drivers/ethernet/wangxun/*

F:	drivers/net/ethernet/wangxun/

F:	drivers/net/pcs/pcs-xpcs-wx.c









WATCHDOG DEVICE DRIVERS









M:	Wim Van Sebroeck <wim@linux-watchdog.org>

























drivers/net/ethernet/wangxun/Kconfig



+1
−0






























Original line number
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@@ -41,6 +41,7 @@ config TXGBE







	tristate "Wangxun(R) 10GbE PCI Express adapters support"









	depends on PCI









	depends on COMMON_CLK









	select MARVELL_10G_PHY









	select REGMAP









	select I2C









	select I2C_DESIGNWARE_PLATFORM
































drivers/net/ethernet/wangxun/libwx/wx_type.h



+28
−0






























Original line number
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@@ -205,6 +205,8 @@







#define WX_TSC_CTL                   0x1D000









#define WX_TSC_CTL_TX_DIS            BIT(1)









#define WX_TSC_CTL_TSEC_DIS          BIT(0)









#define WX_TSC_ST                    0x1D004









#define WX_TSC_ST_SECTX_RDY          BIT(0)









#define WX_TSC_BUF_AE                0x1D00C









#define WX_TSC_BUF_AE_THR            GENMASK(9, 0)


















@@ -231,6 +233,24 @@







#define WX_MAC_WDG_TIMEOUT           0x1100C









#define WX_MAC_RX_FLOW_CTRL          0x11090









#define WX_MAC_RX_FLOW_CTRL_RFE      BIT(0) /* receive fc enable */









/* MDIO Registers */









#define WX_MSCA                      0x11200









#define WX_MSCA_RA(v)                FIELD_PREP(U16_MAX, v)









#define WX_MSCA_PA(v)                FIELD_PREP(GENMASK(20, 16), v)









#define WX_MSCA_DA(v)                FIELD_PREP(GENMASK(25, 21), v)









#define WX_MSCC                      0x11204









#define WX_MSCC_CMD(v)               FIELD_PREP(GENMASK(17, 16), v)



















enum WX_MSCA_CMD_value {









	WX_MSCA_CMD_RSV = 0,









	WX_MSCA_CMD_WRITE,









	WX_MSCA_CMD_POST_READ,









	WX_MSCA_CMD_READ,









};



















#define WX_MSCC_SADDR                BIT(18)









#define WX_MSCC_BUSY                 BIT(22)









#define WX_MDIO_CLK(v)               FIELD_PREP(GENMASK(21, 19), v)









#define WX_MMC_CONTROL               0x11800









#define WX_MMC_CONTROL_RSTONRD       BIT(2) /* reset on read */


















@@ -580,6 +600,13 @@ enum wx_mac_type {







	wx_mac_em









};



















enum sp_media_type {









	sp_media_unknown = 0,









	sp_media_fiber,









	sp_media_copper,









	sp_media_backplane









};



















enum em_mac_type {









	em_mac_type_unknown = 0,









	em_mac_type_mdi,








@@ -827,6 +854,7 @@ struct wx {







	struct wx_bus_info bus;









	struct wx_mac_info mac;









	enum em_mac_type mac_type;









	enum sp_media_type media_type;









	struct wx_eeprom_info eeprom;









	struct wx_addr_filter_info addr_ctrl;









	struct wx_mac_addr *mac_table;
































drivers/net/ethernet/wangxun/ngbe/ngbe_mdio.c



+42
−42






























Original line number
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Diff line







@@ -37,24 +37,24 @@ static int ngbe_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regn

















	wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF);









	/* setup and write the address cycle command */









	command = NGBE_MSCA_RA(regnum) |









		  NGBE_MSCA_PA(phy_addr) |









		  NGBE_MSCA_DA(device_type);









	wr32(wx, NGBE_MSCA, command);









	command = NGBE_MSCC_CMD(NGBE_MSCA_CMD_READ) |









		  NGBE_MSCC_BUSY |









		  NGBE_MDIO_CLK(6);









	wr32(wx, NGBE_MSCC, command);









	command = WX_MSCA_RA(regnum) |









		  WX_MSCA_PA(phy_addr) |









		  WX_MSCA_DA(device_type);









	wr32(wx, WX_MSCA, command);









	command = WX_MSCC_CMD(WX_MSCA_CMD_READ) |









		  WX_MSCC_BUSY |









		  WX_MDIO_CLK(6);









	wr32(wx, WX_MSCC, command);



















	/* wait to complete */









	ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,









				100000, false, wx, NGBE_MSCC);









	ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,









				100000, false, wx, WX_MSCC);









	if (ret) {









		wx_err(wx, "Mdio read c22 command did not complete.\n");









		return ret;









	}



















	return (u16)rd32(wx, NGBE_MSCC);









	return (u16)rd32(wx, WX_MSCC);









}



















static int ngbe_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value)








@@ -65,19 +65,19 @@ static int ngbe_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int reg

















	wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0xF);









	/* setup and write the address cycle command */









	command = NGBE_MSCA_RA(regnum) |









		  NGBE_MSCA_PA(phy_addr) |









		  NGBE_MSCA_DA(device_type);









	wr32(wx, NGBE_MSCA, command);









	command = WX_MSCA_RA(regnum) |









		  WX_MSCA_PA(phy_addr) |









		  WX_MSCA_DA(device_type);









	wr32(wx, WX_MSCA, command);









	command = value |









		  NGBE_MSCC_CMD(NGBE_MSCA_CMD_WRITE) |









		  NGBE_MSCC_BUSY |









		  NGBE_MDIO_CLK(6);









	wr32(wx, NGBE_MSCC, command);









		  WX_MSCC_CMD(WX_MSCA_CMD_WRITE) |









		  WX_MSCC_BUSY |









		  WX_MDIO_CLK(6);









	wr32(wx, WX_MSCC, command);



















	/* wait to complete */









	ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,









				100000, false, wx, NGBE_MSCC);









	ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,









				100000, false, wx, WX_MSCC);









	if (ret)









		wx_err(wx, "Mdio write c22 command did not complete.\n");


















@@ -92,24 +92,24 @@ static int ngbe_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devn

















	wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);









	/* setup and write the address cycle command */









	command = NGBE_MSCA_RA(regnum) |









		  NGBE_MSCA_PA(phy_addr) |









		  NGBE_MSCA_DA(devnum);









	wr32(wx, NGBE_MSCA, command);









	command = NGBE_MSCC_CMD(NGBE_MSCA_CMD_READ) |









		  NGBE_MSCC_BUSY |









		  NGBE_MDIO_CLK(6);









	wr32(wx, NGBE_MSCC, command);









	command = WX_MSCA_RA(regnum) |









		  WX_MSCA_PA(phy_addr) |









		  WX_MSCA_DA(devnum);









	wr32(wx, WX_MSCA, command);









	command = WX_MSCC_CMD(WX_MSCA_CMD_READ) |









		  WX_MSCC_BUSY |









		  WX_MDIO_CLK(6);









	wr32(wx, WX_MSCC, command);



















	/* wait to complete */









	ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,









				100000, false, wx, NGBE_MSCC);









	ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,









				100000, false, wx, WX_MSCC);









	if (ret) {









		wx_err(wx, "Mdio read c45 command did not complete.\n");









		return ret;









	}



















	return (u16)rd32(wx, NGBE_MSCC);









	return (u16)rd32(wx, WX_MSCC);









}



















static int ngbe_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,








@@ -121,19 +121,19 @@ static int ngbe_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr,

















	wr32(wx, NGBE_MDIO_CLAUSE_SELECT, 0x0);









	/* setup and write the address cycle command */









	command = NGBE_MSCA_RA(regnum) |









		  NGBE_MSCA_PA(phy_addr) |









		  NGBE_MSCA_DA(devnum);









	wr32(wx, NGBE_MSCA, command);









	command = WX_MSCA_RA(regnum) |









		  WX_MSCA_PA(phy_addr) |









		  WX_MSCA_DA(devnum);









	wr32(wx, WX_MSCA, command);









	command = value |









		  NGBE_MSCC_CMD(NGBE_MSCA_CMD_WRITE) |









		  NGBE_MSCC_BUSY |









		  NGBE_MDIO_CLK(6);









	wr32(wx, NGBE_MSCC, command);









		  WX_MSCC_CMD(WX_MSCA_CMD_WRITE) |









		  WX_MSCC_BUSY |









		  WX_MDIO_CLK(6);









	wr32(wx, WX_MSCC, command);



















	/* wait to complete */









	ret = read_poll_timeout(rd32, val, !(val & NGBE_MSCC_BUSY), 1000,









				100000, false, wx, NGBE_MSCC);









	ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000,









				100000, false, wx, WX_MSCC);









	if (ret)









		wx_err(wx, "Mdio write c45 command did not complete.\n");










































drivers/net/ethernet/wangxun/ngbe/ngbe_type.h



+0
−19






























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@@ -59,25 +59,6 @@







#define NGBE_EEPROM_VERSION_L			0x1D









#define NGBE_EEPROM_VERSION_H			0x1E



















/* mdio access */









#define NGBE_MSCA				0x11200









#define NGBE_MSCA_RA(v)				FIELD_PREP(U16_MAX, v)









#define NGBE_MSCA_PA(v)				FIELD_PREP(GENMASK(20, 16), v)









#define NGBE_MSCA_DA(v)				FIELD_PREP(GENMASK(25, 21), v)









#define NGBE_MSCC				0x11204









#define NGBE_MSCC_CMD(v)			FIELD_PREP(GENMASK(17, 16), v)



















enum NGBE_MSCA_CMD_value {









	NGBE_MSCA_CMD_RSV = 0,









	NGBE_MSCA_CMD_WRITE,









	NGBE_MSCA_CMD_POST_READ,









	NGBE_MSCA_CMD_READ,









};



















#define NGBE_MSCC_SADDR				BIT(18)









#define NGBE_MSCC_BUSY				BIT(22)









#define NGBE_MDIO_CLK(v)			FIELD_PREP(GENMASK(21, 19), v)



















/* Media-dependent registers. */









#define NGBE_MDIO_CLAUSE_SELECT			0x11220