Commit 8e672b56 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Jakub Kicinski
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net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J784S4 CPSW9G 



TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the
extra_modes member of the J784S4 SoC data.

Configure MAC control register for supporting USXGMII mode and add
MAC_5000FD in the "mac_capabilities" member of struct "phylink_config".

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 4e003d61

drivers/net/ethernet/ti/am65-cpsw-nuss.c

+12 −2
Original line number Diff line number Diff line
@@ -1514,6 +1514,14 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in 
			cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);

		}



		if (state->interface == PHY_INTERFACE_MODE_USXGMII) {

			cpsw_sl_ctl_set(port->slave.mac_sl,

					CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);

		} else {

			cpsw_sl_ctl_clr(port->slave.mac_sl,

					CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN);

		}



		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,

		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);

	}
@@ -2171,7 +2179,8 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 
	/* Configuring Phylink */

	port->slave.phylink_config.dev = &port->ndev->dev;

	port->slave.phylink_config.type = PHYLINK_NETDEV;

	port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;

	port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |

						      MAC_1000FD | MAC_5000FD;

	port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */



	switch (port->slave.phy_if) {
@@ -2189,6 +2198,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 


	case PHY_INTERFACE_MODE_QSGMII:

	case PHY_INTERFACE_MODE_SGMII:

	case PHY_INTERFACE_MODE_USXGMII:

		if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {

			__set_bit(port->slave.phy_if,

				  port->slave.phylink_config.supported_interfaces);
@@ -2814,7 +2824,7 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 
	.quirks = 0,

	.ale_dev_id = "am64-cpswxg",

	.fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),

	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII),

};



static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {