Commit 8e31a949 authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Martin K. Petersen
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scsi: dt-bindings: ufs: ti,j721e-ufs.yaml: Add binding for TI UFS wrapper 

Add binding documentation of TI wrapper for Cadence UFS Controller.

Link: https://lore.kernel.org/r/20191108164857.11466-2-vigneshr@ti.com


Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 0eccce86

Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: TI J721e UFS Host Controller Glue Driver



maintainers:

  - Vignesh Raghavendra <vigneshr@ti.com>



properties:

  compatible:

    items:

      - const: ti,j721e-ufs



  reg:

    maxItems: 1

    description: address of TI UFS glue registers



  clocks:

    maxItems: 1

    description: phandle to the M-PHY clock



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - power-domains



patternProperties:

  "^ufs@[0-9a-f]+$":

    type: object

    description: |

      Cadence UFS controller node must be the child node. Refer

      Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding

      documentation of child node



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    ufs_wrapper: ufs-wrapper@4e80000 {

       compatible = "ti,j721e-ufs";

       reg = <0x0 0x4e80000 0x0 0x100>;

       power-domains = <&k3_pds 277>;

       clocks = <&k3_clks 277 1>;

       assigned-clocks = <&k3_clks 277 1>;

       assigned-clock-parents = <&k3_clks 277 4>;

       #address-cells = <2>;

       #size-cells = <2>;



       ufs@4e84000 {

          compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";

          reg = <0x0 0x4e84000 0x0 0x10000>;

          interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

          freq-table-hz = <19200000 19200000>;

          power-domains = <&k3_pds 277>;

          clocks = <&k3_clks 277 1>;

          assigned-clocks = <&k3_clks 277 1>;

          assigned-clock-parents = <&k3_clks 277 4>;

          clock-names = "core_clk";

       };

    };