Loading drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +2 −0 Original line number Diff line number Diff line Loading @@ -357,6 +357,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; register_pm_notifier(&dev_priv->pm_nb); DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? "Have 3D\n" : "No 3D\n"); return 0; out_no_device: Loading drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +1 −0 Original line number Diff line number Diff line Loading @@ -389,6 +389,7 @@ extern int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence); extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason); extern int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma); extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv); /** * TTM glue - vmwgfx_ttm_glue.c Loading drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +19 −0 Original line number Diff line number Diff line Loading @@ -29,6 +29,25 @@ #include "drmP.h" #include "ttm/ttm_placement.h" bool vmw_fifo_have_3d(struct vmw_private *dev_priv) { __le32 __iomem *fifo_mem = dev_priv->mmio_virt; uint32_t fifo_min, hwversion; fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) return false; hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION); if (hwversion == 0) return false; if (hwversion < SVGA3D_HWVERSION_WS65_B1) return false; return true; } int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) { __le32 __iomem *fifo_mem = dev_priv->mmio_virt; Loading drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +1 −1 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, param->value = vmw_overlay_num_free_overlays(dev_priv); break; case DRM_VMW_PARAM_3D: param->value = dev_priv->capabilities & SVGA_CAP_3D ? 1 : 0; param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0; break; case DRM_VMW_PARAM_FIFO_OFFSET: param->value = dev_priv->mmio_start; Loading Loading
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +2 −0 Original line number Diff line number Diff line Loading @@ -357,6 +357,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; register_pm_notifier(&dev_priv->pm_nb); DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? "Have 3D\n" : "No 3D\n"); return 0; out_no_device: Loading
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +1 −0 Original line number Diff line number Diff line Loading @@ -389,6 +389,7 @@ extern int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence); extern void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason); extern int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma); extern bool vmw_fifo_have_3d(struct vmw_private *dev_priv); /** * TTM glue - vmwgfx_ttm_glue.c Loading
drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +19 −0 Original line number Diff line number Diff line Loading @@ -29,6 +29,25 @@ #include "drmP.h" #include "ttm/ttm_placement.h" bool vmw_fifo_have_3d(struct vmw_private *dev_priv) { __le32 __iomem *fifo_mem = dev_priv->mmio_virt; uint32_t fifo_min, hwversion; fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) return false; hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION); if (hwversion == 0) return false; if (hwversion < SVGA3D_HWVERSION_WS65_B1) return false; return true; } int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) { __le32 __iomem *fifo_mem = dev_priv->mmio_virt; Loading
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +1 −1 Original line number Diff line number Diff line Loading @@ -43,7 +43,7 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, param->value = vmw_overlay_num_free_overlays(dev_priv); break; case DRM_VMW_PARAM_3D: param->value = dev_priv->capabilities & SVGA_CAP_3D ? 1 : 0; param->value = vmw_fifo_have_3d(dev_priv) ? 1 : 0; break; case DRM_VMW_PARAM_FIFO_OFFSET: param->value = dev_priv->mmio_start; Loading