Commit 8e18d065 authored by Zoran Markovic's avatar Zoran Markovic Committed by Stephen Boyd
Browse files

clk: mdm9615: Add EBI2 clock



Add definition of EBI2 clock used by MDM9615 NAND controller.

Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarZoran Markovic <zmarkovic@sierrawireless.com>
Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23]
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 5c48ea1e
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+30 −0
Original line number Diff line number Diff line
@@ -1563,6 +1563,34 @@ static struct clk_branch rpm_msg_ram_h_clk = {
	},
};

static struct clk_branch ebi2_clk = {
	.hwcg_reg = 0x2664,
	.hwcg_bit = 6,
	.halt_reg = 0x2fcc,
	.halt_bit = 24,
	.clkr = {
		.enable_reg = 0x2664,
		.enable_mask = BIT(6) | BIT(4),
		.hw.init = &(struct clk_init_data){
			.name = "ebi2_clk",
			.ops = &clk_branch_ops,
		},
	},
};

static struct clk_branch ebi2_aon_clk = {
	.halt_reg = 0x2fcc,
	.halt_bit = 23,
	.clkr = {
		.enable_reg = 0x2664,
		.enable_mask = BIT(8),
		.hw.init = &(struct clk_init_data){
			.name = "ebi2_aon_clk",
			.ops = &clk_branch_ops,
		},
	},
};

static struct clk_hw *gcc_mdm9615_hws[] = {
	&cxo.hw,
};
@@ -1637,6 +1665,8 @@ static struct clk_regmap *gcc_mdm9615_clks[] = {
	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
	[EBI2_CLK] = &ebi2_clk.clkr,
	[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
};

static const struct qcom_reset_map gcc_mdm9615_resets[] = {
+2 −0
Original line number Diff line number Diff line
@@ -323,5 +323,7 @@
#define CE3_H_CLK				305
#define USB_HS1_SYSTEM_CLK_SRC			306
#define USB_HS1_SYSTEM_CLK			307
#define EBI2_CLK				308
#define EBI2_AON_CLK				309

#endif