Commit 8e11876a authored by Vasant Hegde's avatar Vasant Hegde Committed by Joerg Roedel
Browse files

iommu/amd: Rearrange DTE bit definations 



Rearrage according to 64bit word they are in.

Note that I have not rearranged gcr3 related macros even though
they belong to different 64bit word as its easy to read it in
current format.

No functional changes intended.

Suggested-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230619131908.5887-1-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent bcf847e4

drivers/iommu/amd/amd_iommu_types.h

+4 −4
Original line number Diff line number Diff line
@@ -384,15 +384,15 @@ 
 */

#define DTE_FLAG_V	BIT_ULL(0)

#define DTE_FLAG_TV	BIT_ULL(1)

#define DTE_FLAG_GIOV	BIT_ULL(54)

#define DTE_FLAG_GV	BIT_ULL(55)

#define DTE_GLX_SHIFT	(56)

#define DTE_GLX_MASK	(3)

#define DTE_FLAG_IR	BIT_ULL(61)

#define DTE_FLAG_IW	BIT_ULL(62)



#define DTE_FLAG_IOTLB	BIT_ULL(32)

#define DTE_FLAG_GIOV	BIT_ULL(54)

#define DTE_FLAG_GV	BIT_ULL(55)

#define DTE_FLAG_MASK	(0x3ffULL << 32)

#define DTE_GLX_SHIFT	(56)

#define DTE_GLX_MASK	(3)

#define DEV_DOMID_MASK	0xffffULL



#define DTE_GCR3_VAL_A(x)	(((x) >> 12) & 0x00007ULL)