Commit 8e109590 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.11-2021-01-14' of... 

Merge tag 'amd-drm-fixes-5.11-2021-01-14' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.11-2021-01-14:

amdgpu:
- Update repo location in MAINTAINERS
- Add some new renoir PCI IDs
- Revert CRC UAPI changes
- Revert OLED display fix which cases clocking problems for some systems
- Misc vangogh fixes
- GFX fix for sienna cichlid
- DCN1.0 fix for pipe split
- Fix incorrect PSP command

amdkfd:
- Fix possible out of bounds read in vcrat creation

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210114201354.3998-1-alexander.deucher@amd.com
parents 667d11dc 2f0fa789

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -907,7 +907,7 @@ AMD KFD 
M:	Felix Kuehling <Felix.Kuehling@amd.com>

L:	amd-gfx@lists.freedesktop.org

S:	Supported

T:	git git://people.freedesktop.org/~agd5f/linux

T:	git https://gitlab.freedesktop.org/agd5f/linux.git

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]

F:	drivers/gpu/drm/amd/amdkfd/

F:	drivers/gpu/drm/amd/include/cik_structs.h
@@ -14818,7 +14818,7 @@ M: Alex Deucher <alexander.deucher@amd.com> 
M:	Christian König <christian.koenig@amd.com>

L:	amd-gfx@lists.freedesktop.org

S:	Supported

T:	git git://people.freedesktop.org/~agd5f/linux

T:	git https://gitlab.freedesktop.org/agd5f/linux.git

F:	drivers/gpu/drm/amd/

F:	drivers/gpu/drm/radeon/

F:	include/uapi/drm/amdgpu_drm.h

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+36 −17
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) 
union igp_info {

	struct atom_integrated_system_info_v1_11 v11;

	struct atom_integrated_system_info_v1_12 v12;

	struct atom_integrated_system_info_v2_1 v21;

};



union umc_info {
@@ -209,9 +210,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
		if (adev->flags & AMD_IS_APU) {

			igp_info = (union igp_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (frev) {

			case 1:

				switch (crev) {

				case 11:

				case 12:

					mem_channel_number = igp_info->v11.umachannelnumber;

					if (!mem_channel_number)

						mem_channel_number = 1;

					/* channel width is 64 */

					if (vram_width)

						*vram_width = mem_channel_number * 64;
@@ -219,18 +225,31 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, 
					if (vram_type)

						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);

					break;

			case 12:

				mem_channel_number = igp_info->v12.umachannelnumber;

				default:

					return -EINVAL;

				}

				break;

			case 2:

				switch (crev) {

				case 1:

				case 2:

					mem_channel_number = igp_info->v21.umachannelnumber;

					if (!mem_channel_number)

						mem_channel_number = 1;

					/* channel width is 64 */

					if (vram_width)

						*vram_width = mem_channel_number * 64;

				mem_type = igp_info->v12.memorytype;

					mem_type = igp_info->v21.memorytype;

					if (vram_type)

						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);

					break;

				default:

					return -EINVAL;

				}

				break;

			default:

				return -EINVAL;

			}

		} else {

			vram_info = (union vram_info *)

				(mode_info->atom_context->bios + data_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -3034,7 +3034,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
#endif

	default:

		if (amdgpu_dc > 0)

			DRM_INFO("Display Core has been requested via kernel parameter "

			DRM_INFO_ONCE("Display Core has been requested via kernel parameter "

					 "but isn't supported by ASIC, ignoring\n");

		return false;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −0
Original line number Diff line number Diff line
@@ -1085,6 +1085,8 @@ static const struct pci_device_id pciidlist[] = { 


	/* Renoir */

	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},

	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},

	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},



	/* Navi12 */

	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+46 −2
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ 
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580

#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0



#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1

#define mmSPI_CONFIG_CNTL_1_Vangogh		 0x2441

#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX	 1

#define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
@@ -160,6 +164,9 @@ 
#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db

#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX	0



#define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030

#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0



MODULE_FIRMWARE("amdgpu/navi10_ce.bin");

MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");

MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3324,6 +3331,7 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 
static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);

static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);

static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);

static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);



static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)

{
@@ -7192,6 +7200,9 @@ static int gfx_v10_0_hw_init(void *handle) 
	if (adev->asic_type == CHIP_SIENNA_CICHLID)

		gfx_v10_3_program_pbb_mode(adev);



	if (adev->asic_type >= CHIP_SIENNA_CICHLID)

		gfx_v10_3_set_power_brake_sequence(adev);



	return r;

}
@@ -7377,8 +7388,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 


	amdgpu_gfx_off_ctrl(adev, false);

	mutex_lock(&adev->gfx.gpu_clock_mutex);

	switch (adev->asic_type) {

	case CHIP_VANGOGH:

		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |

			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);

		break;

	default:

		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |

			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);

		break;

	}

	mutex_unlock(&adev->gfx.gpu_clock_mutex);

	amdgpu_gfx_off_ctrl(adev, true);

	return clock;
@@ -9169,6 +9188,31 @@ static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 
	}

}



static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)

{

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,

		     (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |

		     (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |

		     (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));



	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);

	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,

		     (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |

		     (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |

		     (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |

		     (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));



	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,

		     (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |

		     (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |

		     (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));



	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);



	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,

		     (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));

}



const struct amdgpu_ip_block_version gfx_v10_0_ip_block =

{

	.type = AMD_IP_BLOCK_TYPE_GFX,