Commit 8daeaea9 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Jerome Brunet
Browse files

clk: meson: meson8b: make the CCF use the glitch-free mali mux 



The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.

This fixes a potential hang when changing the GPU frequency at runtime.

Fixes: 74e1f252 ("clk: meson: meson8b: add the GPU clock tree")
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent c97fcd85

drivers/clk/meson/meson8b.c

+7 −4
Original line number Diff line number Diff line
@@ -1772,8 +1772,11 @@ static struct clk_regmap meson8b_hdmi_sys = { 


/*

 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)

 * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only

 * has mali_0 and no glitch-free mux.

 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can

 * actually manage this glitch-free mux because it does top-to-bottom

 * updates the each clock tree and switches to the "inactive" one when

 * CLK_SET_RATE_GATE is set.

 * Meson8 only has mali_0 and no glitch-free mux.

 */

static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {

	{ .fw_name = "xtal", .name = "xtal", .index = -1, },
@@ -1838,7 +1841,7 @@ static struct clk_regmap meson8b_mali_0 = { 
			&meson8b_mali_0_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,

	},

};
@@ -1893,7 +1896,7 @@ static struct clk_regmap meson8b_mali_1 = { 
			&meson8b_mali_1_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,

	},

};