Commit 8da32a10 authored by Esben Haabendal's avatar Esben Haabendal Committed by David S. Miller
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net: gianfar: Add definitions for CAR1 and CAM1 register bits 



These are for carry status and interrupt mask bits of statistics registers.

Signed-off-by: default avatarEsben Haabendal <esben@geanix.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e2dbbbe5

drivers/net/ethernet/freescale/gianfar.h

+54 −0
Original line number Diff line number Diff line
@@ -445,6 +445,60 @@ struct ethtool_rx_list { 
#define RQFPR_PER		0x00000002

#define RQFPR_EER		0x00000001



/* CAR1 bits */

#define CAR1_C164		0x80000000

#define CAR1_C1127		0x40000000

#define CAR1_C1255		0x20000000

#define CAR1_C1511		0x10000000

#define CAR1_C11K		0x08000000

#define CAR1_C1MAX		0x04000000

#define CAR1_C1MGV		0x02000000

#define CAR1_C1REJ		0x00020000

#define CAR1_C1RBY		0x00010000

#define CAR1_C1RPK		0x00008000

#define CAR1_C1RFC		0x00004000

#define CAR1_C1RMC		0x00002000

#define CAR1_C1RBC		0x00001000

#define CAR1_C1RXC		0x00000800

#define CAR1_C1RXP		0x00000400

#define CAR1_C1RXU		0x00000200

#define CAR1_C1RAL		0x00000100

#define CAR1_C1RFL		0x00000080

#define CAR1_C1RCD		0x00000040

#define CAR1_C1RCS		0x00000020

#define CAR1_C1RUN		0x00000010

#define CAR1_C1ROV		0x00000008

#define CAR1_C1RFR		0x00000004

#define CAR1_C1RJB		0x00000002

#define CAR1_C1RDR		0x00000001



/* CAM1 bits */

#define CAM1_M164		0x80000000

#define CAM1_M1127		0x40000000

#define CAM1_M1255		0x20000000

#define CAM1_M1511		0x10000000

#define CAM1_M11K		0x08000000

#define CAM1_M1MAX		0x04000000

#define CAM1_M1MGV		0x02000000

#define CAM1_M1REJ		0x00020000

#define CAM1_M1RBY		0x00010000

#define CAM1_M1RPK		0x00008000

#define CAM1_M1RFC		0x00004000

#define CAM1_M1RMC		0x00002000

#define CAM1_M1RBC		0x00001000

#define CAM1_M1RXC		0x00000800

#define CAM1_M1RXP		0x00000400

#define CAM1_M1RXU		0x00000200

#define CAM1_M1RAL		0x00000100

#define CAM1_M1RFL		0x00000080

#define CAM1_M1RCD		0x00000040

#define CAM1_M1RCS		0x00000020

#define CAM1_M1RUN		0x00000010

#define CAM1_M1ROV		0x00000008

#define CAM1_M1RFR		0x00000004

#define CAM1_M1RJB		0x00000002

#define CAM1_M1RDR		0x00000001



/* TxBD status field bits */

#define TXBD_READY		0x8000

#define TXBD_PADCRC		0x4000