Commit 8da1170a authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher
Browse files

drm/amdgpu: add VCN4 ip block support



Add VCN 4.0 initialization and decoder/encoder ring functions.

Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19dc81b4
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+1 −0
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@@ -171,6 +171,7 @@ amdgpu-y += \
	vcn_v2_0.o \
	vcn_v2_5.o \
	vcn_v3_0.o \
	vcn_v4_0.o \
	amdgpu_jpeg.o \
	jpeg_v1_0.o \
	jpeg_v2_0.o \
+17 −2
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@@ -53,6 +53,7 @@
#define FIRMWARE_BEIGE_GOBY	"amdgpu/beige_goby_vcn.bin"
#define FIRMWARE_YELLOW_CARP	"amdgpu/yellow_carp_vcn.bin"
#define FIRMWARE_VCN_3_1_2	"amdgpu/vcn_3_1_2.bin"
#define FIRMWARE_VCN4_0_0	"amdgpu/vcn_4_0_0.bin"

MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
@@ -71,6 +72,7 @@ MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);

static void amdgpu_vcn_idle_work_handler(struct work_struct *work);

@@ -175,6 +177,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
			adev->vcn.indirect_sram = true;
		break;
	case IP_VERSION(4, 0, 0):
		fw_name = FIRMWARE_VCN4_0_0;
		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
			(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
			adev->vcn.indirect_sram = true;
		break;
	default:
		return -EINVAL;
	}
@@ -228,8 +236,15 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);

	if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){
		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
		log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
	} else {
		fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
		log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
	}

	bo_size += fw_shared_size;

	if (amdgpu_vcnfw_log)
+16 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@
		}										\
	} while (0)

#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)
#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB	(1 << 6)
#define AMDGPU_VCN_MULTI_QUEUE_FLAG	(1 << 8)
#define AMDGPU_VCN_SW_RING_FLAG		(1 << 9)
@@ -286,6 +287,13 @@ struct amdgpu_fw_shared_sw_ring {
	uint8_t padding[3];
};

struct amdgpu_fw_shared_unified_queue_struct {
	uint8_t is_enabled;
	uint8_t queue_mode;
	uint8_t queue_status;
	uint8_t padding[5];
};

struct amdgpu_fw_shared_fw_logging {
	uint8_t is_enabled;
	uint32_t addr_lo;
@@ -309,6 +317,14 @@ struct amdgpu_fw_shared {
	struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
};

struct amdgpu_vcn4_fw_shared {
	uint32_t present_flag_0;
	uint8_t pad[12];
	struct amdgpu_fw_shared_unified_queue_struct sq;
	uint8_t pad1[8];
	struct amdgpu_fw_shared_fw_logging fw_log;
};

struct amdgpu_vcn_fwlog {
	uint32_t rptr;
	uint32_t wptr;
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/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __VCN_V4_0_H__
#define __VCN_V4_0_H__

extern const struct amdgpu_ip_block_version vcn_v4_0_ip_block;

#endif /* __VCN_V4_0_H__ */