Commit 8da046fe authored by Haoyue Xu's avatar Haoyue Xu Committed by Zheng Zengkai
Browse files

RDMA/hns: Remove unused abnormal interrupt of type RAS

mainline inclusion
from mainline-for-next
commit f5c25465
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5IZO5
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git/commit/?id=f5c25465b4f7d3badcaa5bf4a6f82f5763865b19

----------------------------------------------------------------------

The HNS NIC driver receives and handles the abnormal interrupt of the RAS
type generated by ROCEE, and the HNS RDMA driver does not need to handle
this type of interrupt. Therefore, delete unused codes in the HNS RDMA
driver.

Link: https://lore.kernel.org/r/20220714134353.16700-2-liangwenpeng@huawei.com


Signed-off-by: default avatarHaoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
Signed-off-by: default avatarZhengfeng Luo <luozhengfeng@h-partners.com>
Reviewed-by: default avatarYangyang Li <liyangyang20@huawei.com>
Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 82f0fe0b
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Original line number Diff line number Diff line
@@ -5659,16 +5659,6 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
		int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);

		int_work = 1;
	} else if (int_st & BIT(HNS_ROCE_V2_VF_INT_ST_RAS_INT_S)) {
		dev_err(dev, "RAS interrupt!\n");

		int_st |= 1 << HNS_ROCE_V2_VF_INT_ST_RAS_INT_S;
		roce_write(hr_dev, ROCEE_VF_ABN_INT_ST_REG, int_st);

		int_en |= 1 << HNS_ROCE_V2_VF_ABN_INT_EN_S;
		roce_write(hr_dev, ROCEE_VF_ABN_INT_EN_REG, int_en);

		int_work = 1;
	} else {
		dev_err(dev, "There is no abnormal irq found!\n");
+0 −1
Original line number Diff line number Diff line
@@ -1354,7 +1354,6 @@ struct hns_roce_dip {
#define HNS_ROCE_V2_ASYNC_EQE_NUM		0x1000

#define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S	0
#define HNS_ROCE_V2_VF_INT_ST_RAS_INT_S		1

#define HNS_ROCE_EQ_DB_CMD_AEQ			0x0
#define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED		0x1