Commit 8d8ccdd2 authored by Jason-JH.Lin's avatar Jason-JH.Lin Committed by Matthias Brugger
Browse files

Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0" 



This reverts commit b804923b.

Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.

Signed-off-by: default avatarJason-JH.Lin <jason-jh.lin@mediatek.com>
Link: https://lore.kernel.org/r/20220927152704.12018-3-jason-jh.lin@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent b237efd4

drivers/soc/mediatek/mt8195-mmsys.h

deleted100644 → 0
+0 −370
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H

#define __SOC_MEDIATEK_MT8195_MMSYS_H



#define MT8195_VDO0_OVL_MOUT_EN					0xf14

#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)

#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)

#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)

#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)

#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)

#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)



#define MT8195_VDO0_SEL_IN					0xf34

#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)

#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)

#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)

#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)

#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)

#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)

#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)

#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)

#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)

#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)

#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)

#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)

#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)

#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)

#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)

#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)

#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)

#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)

#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)

#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)

#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)

#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)

#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)

#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)

#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)

#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)

#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)

#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)

#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)

#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)

#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)

#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)

#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)



#define MT8195_VDO0_SEL_OUT					0xf38

#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)

#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)

#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)

#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)

#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)

#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)

#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)

#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)

#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)

#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)

#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)

#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)

#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)

#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)

#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)

#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)

#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)

#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)

#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)

#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)

#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)

#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)

#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)



static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,

		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,

		MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,

		MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,

		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,

		MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,

		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,

		MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,

		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,

		MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,

		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,

		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,

		MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,

		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,

		MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,

		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,

		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,

		MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,

		MT8195_SEL_IN_DSI1_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,

		MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,

		MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,

		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,

		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,

		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,

		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN

	}, {

		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,

		MT8195_SOUT_DISP_DITHER0_TO_DSI0

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,

		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT

	}, {

		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,

		MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE

	}, {

		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,

		MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_DSI1

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,

		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN

	}, {

		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,

		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0

	}, {

		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,

		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,

		MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE

	}

};



#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

drivers/soc/mediatek/mtk-mmsys.c

+11 −141
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 
#include "mt8183-mmsys.h"

#include "mt8186-mmsys.h"

#include "mt8192-mmsys.h"

#include "mt8195-mmsys.h"

#include "mt8365-mmsys.h"



static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -26,61 +25,26 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 
	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),

};



static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt2701_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {

	.clk_driver = "clk-mt2712-mm",

	.routes = mmsys_default_routing_table,

	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),

};



static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt2712_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {

	.clk_driver = "clk-mt6779-mm",

};



static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt6779_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {

	.clk_driver = "clk-mt6797-mm",

};



static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt6797_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {

	.clk_driver = "clk-mt8167-mm",

	.routes = mt8167_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),

};



static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8167_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {

	.clk_driver = "clk-mt8173-mm",

	.routes = mmsys_default_routing_table,
@@ -88,13 +52,6 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 
	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,

};



static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8173_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {

	.clk_driver = "clk-mt8183-mm",

	.routes = mmsys_mt8183_routing_table,
@@ -102,13 +59,6 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { 
	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,

};



static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8183_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {

	.clk_driver = "clk-mt8186-mm",

	.routes = mmsys_mt8186_routing_table,
@@ -116,13 +66,6 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { 
	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,

};



static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8186_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {

	.clk_driver = "clk-mt8192-mm",

	.routes = mmsys_mt8192_routing_table,
@@ -130,66 +73,19 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { 
	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,

};



static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8192_mmsys_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {

	.io_start = 0x1c01a000,

	.clk_driver = "clk-mt8195-vdo0",

	.routes = mmsys_mt8195_routing_table,

	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),

};



static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {

	.io_start = 0x1c100000,

	.clk_driver = "clk-mt8195-vdo1",

};



static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {

	.num_drv_data = 2,

	.drv_data = {

		&mt8195_vdosys0_driver_data,

		&mt8195_vdosys1_driver_data,

	},

};



static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {

	.clk_driver = "clk-mt8365-mm",

	.routes = mt8365_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),

};



static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {

	.num_drv_data = 1,

	.drv_data = {

		&mt8365_mmsys_driver_data,

	},

};



struct mtk_mmsys {

	void __iomem *regs;

	const struct mtk_mmsys_driver_data *data;

	spinlock_t lock; /* protects mmsys_sw_rst_b reg */

	struct reset_controller_dev rcdev;

	phys_addr_t io_start;

};



static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,

					const struct mtk_mmsys_match_data *match)

{

	int i;



	for (i = 0; i < match->num_drv_data; i++)

		if (mmsys->io_start == match->drv_data[i]->io_start)

			return i;



	return -EINVAL;

}



void mtk_mmsys_ddp_connect(struct device *dev,

			   enum mtk_ddp_comp_id cur,

			   enum mtk_ddp_comp_id next)
@@ -319,9 +215,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
	struct device *dev = &pdev->dev;

	struct platform_device *clks;

	struct platform_device *drm;

	const struct mtk_mmsys_match_data *match_data;

	struct mtk_mmsys *mmsys;

	struct resource *res;

	int ret;



	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -347,27 +241,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
		return ret;

	}



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res) {

		dev_err(dev, "Couldn't get mmsys resource\n");

		return -EINVAL;

	}

	mmsys->io_start = res->start;



	match_data = of_device_get_match_data(dev);

	if (match_data->num_drv_data > 1) {

		/* This SoC has multiple mmsys channels */

		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);

		if (ret < 0) {

			dev_err(dev, "Couldn't get match driver data\n");

			return ret;

		}

		mmsys->data = match_data->drv_data[ret];

	} else {

		dev_dbg(dev, "Using single mmsys channel\n");

		mmsys->data = match_data->drv_data[0];

	}



	mmsys->data = of_device_get_match_data(&pdev->dev);

	platform_set_drvdata(pdev, mmsys);



	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -388,47 +262,43 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
static const struct of_device_id of_match_mtk_mmsys[] = {

	{

		.compatible = "mediatek,mt2701-mmsys",

		.data = &mt2701_mmsys_match_data,

		.data = &mt2701_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt2712-mmsys",

		.data = &mt2712_mmsys_match_data,

		.data = &mt2712_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt6779-mmsys",

		.data = &mt6779_mmsys_match_data,

		.data = &mt6779_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt6797-mmsys",

		.data = &mt6797_mmsys_match_data,

		.data = &mt6797_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8167-mmsys",

		.data = &mt8167_mmsys_match_data,

		.data = &mt8167_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8173-mmsys",

		.data = &mt8173_mmsys_match_data,

		.data = &mt8173_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8183-mmsys",

		.data = &mt8183_mmsys_match_data,

		.data = &mt8183_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8186-mmsys",

		.data = &mt8186_mmsys_match_data,

		.data = &mt8186_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8192-mmsys",

		.data = &mt8192_mmsys_match_data,

	},

	{

		.compatible = "mediatek,mt8195-mmsys",

		.data = &mt8195_mmsys_match_data,

		.data = &mt8192_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8365-mmsys",

		.data = &mt8365_mmsys_match_data,

		.data = &mt8365_mmsys_driver_data,

	},

	{ }

};

drivers/soc/mediatek/mtk-mmsys.h

+0 −6
Original line number Diff line number Diff line
@@ -87,18 +87,12 @@ struct mtk_mmsys_routes { 
};



struct mtk_mmsys_driver_data {

	const resource_size_t io_start;

	const char *clk_driver;

	const struct mtk_mmsys_routes *routes;

	const unsigned int num_routes;

	const u16 sw0_rst_offset;

};



struct mtk_mmsys_match_data {

	unsigned short num_drv_data;

	const struct mtk_mmsys_driver_data *drv_data[];

};



/*

 * Routes in mt8173, mt2701, mt2712 are different. That means

 * in the same register address, it controls different input/output