Commit 8d741ecd authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-imx', 'clk-ux500' and 'clk-debugfs' into clk-next 

* clk-imx: (21 commits)
  clk: imx: Make CLK_IMX8ULP select MXC_CLK
  clk: imx: imx6ul: Fix csi clk gate register
  clk: imx: imx6ul: Move csi_sel mux to correct base register
  clk: imx: Fix the build break when clk-imx8ulp build as module
  clk: imx: Add the pcc reset controller support on imx8ulp
  clk: imx: Add clock driver for imx8ulp
  clk: imx: Update the pfdv2 for 8ulp specific support
  clk: imx: disable the pfd when set pfdv2 clock rate
  clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp
  clk: imx: disable i.mx7ulp composite clock during initialization
  clk: imx: Update the compsite driver to support imx8ulp
  clk: imx: Update the pllv4 to support imx8ulp
  dt-bindings: clock: Add imx8ulp clock support
  clk: imx: Rework imx_clk_hw_pll14xx wrapper
  clk: imx: Rework all imx_clk_hw_composite wrappers
  clk: imx: Rework all clk_hw_register_divider wrappers
  clk: imx: Rework all clk_hw_register_mux wrappers
  clk: imx: Rework all clk_hw_register_gate2 wrappers
  clk: imx: Rework all clk_hw_register_gate wrappers
  clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones
  ...

* clk-ux500:
  clk: ux500: Add driver for the reset portions of PRCC
  dt-bindings: clock: u8500: Rewrite in YAML and extend

* clk-debugfs:
  clk: use clk_core_get_rate_recalc() in clk_rate_get()
parents b43e2d55 897a54f9 b14cbdfd dd742cac

Documentation/devicetree/bindings/clock/imx8ulp-cgc-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding



maintainers:

  - Jacky Bai <ping.bai@nxp.com>



description: |

  On i.MX8ULP, The clock sources generation, distribution and management is

  under the control of several CGCs & PCCs modules. The CGC modules generate

  and distribute clocks on the device.



properties:

  compatible:

    enum:

      - fsl,imx8ulp-cgc1

      - fsl,imx8ulp-cgc2



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock Generation & Control Module node:

  - |

    clock-controller@292c0000 {

        compatible = "fsl,imx8ulp-cgc1";

        reg = <0x292c0000 0x10000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/imx8ulp-pcc-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding



maintainers:

  - Jacky Bai <ping.bai@nxp.com>



description: |

  On i.MX8ULP, The clock sources generation, distribution and management is

  under the control of several CGCs & PCCs modules. The PCC modules control

  software reset, clock selection, optional division and clock gating mode

  for peripherals.



properties:

  compatible:

    enum:

      - fsl,imx8ulp-pcc3

      - fsl,imx8ulp-pcc4

      - fsl,imx8ulp-pcc5



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  # Peripheral Clock Control Module node:

  - |

    clock-controller@292d0000 {

        compatible = "fsl,imx8ulp-pcc3";

        reg = <0x292d0000 0x10000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ST-Ericsson DB8500 (U8500) clocks



maintainers:

  - Ulf Hansson <ulf.hansson@linaro.org>

  - Linus Walleij <linus.walleij@linaro.org>



description: While named "U8500 clocks" these clocks are inside the

  DB8500 digital baseband system-on-chip and its siblings such as

  DB8520. These bindings consider the clocks present in the SoC

  itself, not off-chip clocks. There are four different on-chip

  clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and

  control management unit) clocks and PRCC (peripheral reset and

  clock controller) clocks. For some reason PRCC 4 does not exist so

  the itemization can be a bit unintuitive.



properties:

  compatible:

    enum:

      - stericsson,u8500-clks

      - stericsson,u8540-clks

      - stericsson,u9540-clks



  reg:

    items:

      - description: PRCC 1 register area

      - description: PRCC 2 register area

      - description: PRCC 3 register area

      - description: PRCC 5 register area

      - description: PRCC 6 register area



  prcmu-clock:

    description: A subnode with one clock cell for PRCMU (power, reset, control

      management unit) clocks. The cell indicates which PRCMU clock in the

      prcmu-clock node the consumer wants to use.

    type: object



    properties:

      '#clock-cells':

        const: 1



    additionalProperties: false



  prcc-periph-clock:

    description: A subnode with two clock cells for PRCC (peripheral

      reset and clock controller) peripheral clocks. The first cell indicates

      which PRCC block the consumer wants to use, possible values are 1, 2, 3,

      5, 6. The second cell indicates which clock inside the PRCC block it

      wants, possible values are 0 thru 31.

    type: object



    properties:

      '#clock-cells':

        const: 2



    additionalProperties: false



  prcc-kernel-clock:

    description: A subnode with two clock cells for PRCC (peripheral reset

      and clock controller) kernel clocks. The first cell indicates which PRCC

      block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The

      second cell indicates which clock inside the PRCC block it wants, possible

      values are 0 thru 31.

    type: object



    properties:

      '#clock-cells':

        const: 2



    additionalProperties: false



  prcc-reset-controller:

    description: A subnode with two reset cells for the reset portions of the

      PRCC (peripheral reset and clock controller). The first cell indicates

      which PRCC block the consumer wants to use, possible values are 1, 2, 3

      5 and 6. The second cell indicates which reset line inside the PRCC block

      it wants to control, possible values are 0 thru 31.

    type: object



    properties:

      '#reset-cells':

        const: 2



    additionalProperties: false



  rtc32k-clock:

    description: A subnode with zero clock cells for the 32kHz RTC clock.

    type: object



    properties:

      '#clock-cells':

        const: 0



    additionalProperties: false



  smp-twd-clock:

    description: A subnode for the ARM SMP Timer Watchdog cluster with zero

      clock cells.

    type: object



    properties:

      '#clock-cells':

        const: 0



    additionalProperties: false



required:

  - compatible

  - reg

  - prcmu-clock

  - prcc-periph-clock

  - prcc-kernel-clock

  - rtc32k-clock

  - smp-twd-clock



additionalProperties: false

Documentation/devicetree/bindings/clock/ux500.txt

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Clock bindings for ST-Ericsson Ux500 clocks



Required properties :

- compatible : shall contain only one of the following:

  "stericsson,u8500-clks"

  "stericsson,u8540-clks"

  "stericsson,u9540-clks"

- reg : shall contain base register location and length for

  CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of

  CLKRST4, which does not exist.



Required subnodes:

- prcmu-clock: a subnode with one clock cell for PRCMU (power,

  reset, control unit) clocks. The cell indicates which PRCMU

  clock in the prcmu-clock node the consumer wants to use.

- prcc-periph-clock: a subnode with two clock cells for

  PRCC (programmable reset- and clock controller) peripheral clocks.

  The first cell indicates which PRCC block the consumer

  wants to use, possible values are 1, 2, 3, 5, 6. The second

  cell indicates which clock inside the PRCC block it wants,

  possible values are 0 thru 31.

- prcc-kernel-clock: a subnode with two clock cells for

  PRCC (programmable reset- and clock controller) kernel clocks

  The first cell indicates which PRCC block the consumer

  wants to use, possible values are 1, 2, 3, 5, 6. The second

  cell indicates which clock inside the PRCC block it wants,

  possible values are 0 thru 31.

- rtc32k-clock: a subnode with zero clock cells for the 32kHz

  RTC clock.

- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster

  with zero clock cells.



Example:



clocks {

	compatible = "stericsson,u8500-clks";

	/*

	 * Registers for the CLKRST block on peripheral

	 * groups 1, 2, 3, 5, 6,

	 */

	reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,

	    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,

	    <0xa03cf000 0x1000>;



	prcmu_clk: prcmu-clock {

		#clock-cells = <1>;

	};



	prcc_pclk: prcc-periph-clock {

		#clock-cells = <2>;

	};



	prcc_kclk: prcc-kernel-clock {

		#clock-cells = <2>;

	};



	rtc_clk: rtc32k-clock {

		#clock-cells = <0>;

	};



	smp_twd_clk: smp-twd-clock {

		#clock-cells = <0>;

	};

};

arch/arm/mach-ux500/Kconfig

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@@ -29,6 +29,7 @@ menuconfig ARCH_U8500 
	select REGULATOR_DB8500_PRCMU

	select REGULATOR_FIXED_VOLTAGE

	select SOC_BUS

	select RESET_CONTROLLER

	help

	  Support for ST-Ericsson's Ux500 architecture