Commit 8d71c78e authored by Thomas Zimmermann's avatar Thomas Zimmermann
Browse files

Merge drm/drm-next into drm-misc-next 



Backmerging to sync with other DRM trees.

Signed-off-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
parents 0c8fb246 68de345e

Documentation/gpu/amdgpu/apu-asic-info-table.csv

+10 −8
Original line number Diff line number Diff line 
Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version

Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0

Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1

SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1

Ryzen 5000 series, GREEN SARDINE, DCN 2.1, 9.3, VCN 2.2, 4.1.1

Ryzen 6000 Zen, YELLOW CARP, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3
 
Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 version

Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3, n/a

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0, 10.0.0

Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3

Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1, 10.0.1

SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0

Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1

Ryzen 6000 series / Ryzen 7x35 series, YELLOW CARP / Rembrandt / Rembrandt+, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3

Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5

Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8

Documentation/gpu/amdgpu/dgpu-asic-info-table.csv

+2 −0
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@@ -22,3 +22,5 @@ AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 
AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2

AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4

AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5

AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0

AMD Radeon RX 7600M (XT) /7700S /7600S, , DCN 3.2.1, 11.0.2, VCN 4.0.4, 6.0.2

Documentation/gpu/amdgpu/driver-misc.rst

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ Accelerated Processing Units (APU) Info 


.. csv-table::

   :header-rows: 1

   :widths: 3, 2, 2, 1, 1, 1

   :widths: 3, 2, 2, 1, 1, 1, 1

   :file: ./apu-asic-info-table.csv



Discrete GPU Info

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ amdgpu-y += \ 
	gfx_v10_0.o \

	imu_v11_0.o \

	gfx_v11_0.o \

	gfx_v11_0_3.o \

	imu_v11_0_3.o



# add async DMA block

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+7 −3
Original line number Diff line number Diff line
@@ -2076,6 +2076,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
	struct drm_device *dev = adev_to_drm(adev);

	struct pci_dev *parent;

	int i, r;

	bool total;



	amdgpu_device_enable_virtual_display(adev);
@@ -2159,6 +2160,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)

		adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;



	total = true;

	for (i = 0; i < adev->num_ip_blocks; i++) {

		if ((amdgpu_ip_block_mask & (1 << i)) == 0) {

			DRM_ERROR("disabled ip block: %d <%s>\n",
@@ -2172,7 +2174,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 
				} else if (r) {

					DRM_ERROR("early_init of IP block <%s> failed %d\n",

						  adev->ip_blocks[i].version->funcs->name, r);

					return r;

					total = false;

				} else {

					adev->ip_blocks[i].status.valid = true;

				}
@@ -2203,6 +2205,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) 


		}

	}

	if (!total)

		return -ENODEV;



	adev->cg_flags &= amdgpu_cg_mask;

	adev->pg_flags &= amdgpu_pg_mask;