Commit 8d6c65bd authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Rob Herring
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dt-bindings: memory-controllers: renesas,dbsc: Convert to json-schema 



Convert the Renesas DDR Bus Controller Device Tree binding documentation
to json-schema.

Drop referrals to driver behavior.
Make power-domains required, as it is present for all current users.
Update the example to match reality.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent c95d5e13

Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt

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DT bindings for Renesas R-Mobile and SH-Mobile memory controllers

=================================================================



Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.

These memory controllers differ from one SoC variant to another, and are called

by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller

(DBSC3)", "SDRAM Bus State Controller (SBSC)").



Currently memory controller device nodes are used only to reference PM

domains, and prevent these PM domains from being powered down, which would

crash the system.



As there exist no actual drivers for these controllers yet, these bindings

should be considered EXPERIMENTAL for now.



Required properties:

  - compatible: Must be one of the following SoC-specific values:

		  - "renesas,dbsc-r8a73a4" (R-Mobile APE6)

		  - "renesas,dbsc3-r8a7740" (R-Mobile A1)

		  - "renesas,sbsc-sh73a0" (SH-Mobile AG5)

  - reg: Must contain the base address and length of the memory controller's

	 registers.



Optional properties:

  - interrupts: Must contain a list of interrupt specifiers for memory

		controller interrupts, if available.

  - interrupt-names: Must contain a list of interrupt names corresponding to

		     the interrupts in the interrupts property, if available.

		     Valid interrupt names are:

			- "sec" (secure interrupt)

			- "temp" (normal (temperature) interrupt)

  - power-domains: Must contain a reference to the PM domain that the memory

		   controller belongs to, if available.



Example:



	sbsc1: memory-controller@fe400000 {

		compatible = "renesas,sbsc-sh73a0";

		reg = <0xfe400000 0x400>;

		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,

			     <0 36 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "sec", "temp";

		power-domains = <&pd_a4bc0>;

	};

Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas DDR Bus Controllers



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  Renesas SoCs contain one or more memory controllers.  These memory

  controllers differ from one SoC variant to another, and are called by

  different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller

  (DBSC3)", or "SDRAM Bus State Controller (SBSC)").



properties:

  compatible:

    enum:

      - renesas,dbsc-r8a73a4  # R-Mobile APE6

      - renesas,dbsc3-r8a7740 # R-Mobile A1

      - renesas,sbsc-sh73a0   # SH-Mobile AG5



  reg:

    maxItems: 1



  interrupts:

    maxItems: 2



  interrupt-names:

    items:

      - const: sec  # secure interrupt

      - const: temp # normal (temperature) interrupt



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sbsc1: memory-controller@fe400000 {

            compatible = "renesas,sbsc-sh73a0";

            reg = <0xfe400000 0x400>;

            interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "sec", "temp";

            power-domains = <&pd_a4bc0>;

    };