Commit 8d56e5c5 authored by Alexandru Elisei's avatar Alexandru Elisei Committed by Catalin Marinas
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arm64: Treat ESR_ELx as a 64-bit register 

In the initial release of the ARM Architecture Reference Manual for
ARMv8-A, the ESR_ELx registers were defined as 32-bit registers. This
changed in 2018 with version D.a (ARM DDI 0487D.a) of the architecture,
when they became 64-bit registers, with bits [63:32] defined as RES0. In
version G.a, a new field was added to ESR_ELx, ISS2, which covers bits
[36:32].  This field is used when the Armv8.7 extension FEAT_LS64 is
implemented.

As a result of the evolution of the register width, Linux stores it as
both a 64-bit value and a 32-bit value, which hasn't affected correctness
so far as Linux only uses the lower 32 bits of the register.

Make the register type consistent and always treat it as 64-bit wide. The
register is redefined as an "unsigned long", which is an unsigned
double-word (64-bit quantity) for the LP64 machine (aapcs64 [1], Table 1,
page 14). The type was chosen because "unsigned int" is the most frequent
type for ESR_ELx and because FAR_ELx, which is used together with ESR_ELx
in exception handling, is also declared as "unsigned long". The 64-bit type
also makes adding support for architectural features that use fields above
bit 31 easier in the future.

The KVM hypervisor will receive a similar update in a subsequent patch.

[1] https://github.com/ARM-software/abi-aa/releases/download/2021Q3/aapcs64.pdf



Signed-off-by: default avatarAlexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220425114444.368693-4-alexandru.elisei@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 3fed9e55

arch/arm64/include/asm/debug-monitors.h

+2 −2
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ struct task_struct; 


struct step_hook {

	struct list_head node;

	int (*fn)(struct pt_regs *regs, unsigned int esr);

	int (*fn)(struct pt_regs *regs, unsigned long esr);

};



void register_user_step_hook(struct step_hook *hook);
@@ -75,7 +75,7 @@ void unregister_kernel_step_hook(struct step_hook *hook); 


struct break_hook {

	struct list_head node;

	int (*fn)(struct pt_regs *regs, unsigned int esr);

	int (*fn)(struct pt_regs *regs, unsigned long esr);

	u16 imm;

	u16 mask; /* These bits are ignored when comparing with imm */

};

arch/arm64/include/asm/esr.h

+3 −3
Original line number Diff line number Diff line
@@ -330,14 +330,14 @@ 
#ifndef __ASSEMBLY__

#include <asm/types.h>



static inline bool esr_is_data_abort(u32 esr)

static inline bool esr_is_data_abort(unsigned long esr)

{

	const u32 ec = ESR_ELx_EC(esr);

	const unsigned long ec = ESR_ELx_EC(esr);



	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;

}



const char *esr_get_class_string(u32 esr);

const char *esr_get_class_string(unsigned long esr);

#endif /* __ASSEMBLY */



#endif /* __ASM_ESR_H */

arch/arm64/include/asm/exception.h

+14 −14
Original line number Diff line number Diff line
@@ -19,9 +19,9 @@ 
#define __exception_irq_entry	__kprobes

#endif



static inline u32 disr_to_esr(u64 disr)

static inline unsigned long disr_to_esr(u64 disr)

{

	unsigned int esr = ESR_ELx_EC_SERROR << ESR_ELx_EC_SHIFT;

	unsigned long esr = ESR_ELx_EC_SERROR << ESR_ELx_EC_SHIFT;



	if ((disr & DISR_EL1_IDS) == 0)

		esr |= (disr & DISR_EL1_ESR_MASK);
@@ -57,23 +57,23 @@ asmlinkage void call_on_irq_stack(struct pt_regs *regs, 
				  void (*func)(struct pt_regs *));

asmlinkage void asm_exit_to_user_mode(struct pt_regs *regs);



void do_mem_abort(unsigned long far, unsigned int esr, struct pt_regs *regs);

void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *regs);

void do_undefinstr(struct pt_regs *regs);

void do_bti(struct pt_regs *regs);

void do_debug_exception(unsigned long addr_if_watchpoint, unsigned int esr,

void do_debug_exception(unsigned long addr_if_watchpoint, unsigned long esr,

			struct pt_regs *regs);

void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs);

void do_sve_acc(unsigned int esr, struct pt_regs *regs);

void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs);

void do_sysinstr(unsigned int esr, struct pt_regs *regs);

void do_sp_pc_abort(unsigned long addr, unsigned int esr, struct pt_regs *regs);

void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr);

void do_cp15instr(unsigned int esr, struct pt_regs *regs);

void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs);

void do_sve_acc(unsigned long esr, struct pt_regs *regs);

void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs);

void do_sysinstr(unsigned long esr, struct pt_regs *regs);

void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs);

void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr);

void do_cp15instr(unsigned long esr, struct pt_regs *regs);

void do_el0_svc(struct pt_regs *regs);

void do_el0_svc_compat(struct pt_regs *regs);

void do_ptrauth_fault(struct pt_regs *regs, unsigned int esr);

void do_serror(struct pt_regs *regs, unsigned int esr);

void do_ptrauth_fault(struct pt_regs *regs, unsigned long esr);

void do_serror(struct pt_regs *regs, unsigned long esr);

void do_notify_resume(struct pt_regs *regs, unsigned long thread_flags);



void panic_bad_stack(struct pt_regs *regs, unsigned int esr, unsigned long far);

void panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far);

#endif	/* __ASM_EXCEPTION_H */

arch/arm64/include/asm/system_misc.h

+2 −2
Original line number Diff line number Diff line
@@ -23,9 +23,9 @@ void die(const char *msg, struct pt_regs *regs, int err); 
struct siginfo;

void arm64_notify_die(const char *str, struct pt_regs *regs,

		      int signo, int sicode, unsigned long far,

		      int err);

		      unsigned long err);



void hook_debug_fault_code(int nr, int (*fn)(unsigned long, unsigned int,

void hook_debug_fault_code(int nr, int (*fn)(unsigned long, unsigned long,

					     struct pt_regs *),

			   int sig, int code, const char *name);

arch/arm64/include/asm/traps.h

+6 −6
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ struct undef_hook { 


void register_undef_hook(struct undef_hook *hook);

void unregister_undef_hook(struct undef_hook *hook);

void force_signal_inject(int signal, int code, unsigned long address, unsigned int err);

void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);

void arm64_notify_segfault(unsigned long addr);

void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);

void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
@@ -57,7 +57,7 @@ static inline int in_entry_text(unsigned long ptr) 
 * errors share the same encoding as an all-zeros encoding from a CPU that

 * doesn't support RAS.

 */

static inline bool arm64_is_ras_serror(u32 esr)

static inline bool arm64_is_ras_serror(unsigned long esr)

{

	WARN_ON(preemptible());
@@ -77,9 +77,9 @@ static inline bool arm64_is_ras_serror(u32 esr) 
 * We treat them as Uncontainable.

 * Non-RAS SError's are reported as Uncontained/Uncategorized.

 */

static inline u32 arm64_ras_serror_get_severity(u32 esr)

static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)

{

	u32 aet = esr & ESR_ELx_AET;

	unsigned long aet = esr & ESR_ELx_AET;



	if (!arm64_is_ras_serror(esr)) {

		/* Not a RAS error, we can't interpret the ESR. */
@@ -98,6 +98,6 @@ static inline u32 arm64_ras_serror_get_severity(u32 esr) 
	return aet;

}



bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr);

void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr);

bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);

void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);

#endif