Commit 8d4cc92b authored by Yufeng Mo's avatar Yufeng Mo Committed by Zheng Zengkai
Browse files

net: hns3: add support for obtaining the maximum frame size 

mainline inclusion
from mainline-v5.12-rc1-dontuse
commit e070c8b9
category: feature
bugzilla: 173966
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e070c8b91ac1c7810c8448b1e5534d1895a0c7f4



----------------------------------------------------------------------

Since the newer hardware may supports different frame size,
so add support to obtain the capability from the firmware
instead of the fixed value.

Signed-off-by: default avatarYufeng Mo <moyufeng@huawei.com>
Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Reviewed-by: default avatarYongxin Li <liyongxin1@huawei.com>
Signed-off-by: default avatarJunxin Chen <chenjunxin1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 1d03b14f

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+1 −0
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ struct hnae3_dev_specs { 
	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */

	u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */

	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */

	u16 max_frm_size;

};



struct hnae3_client_ops {

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+1 −0
Original line number Diff line number Diff line
@@ -389,6 +389,7 @@ static void hns3_dbg_dev_specs(struct hnae3_handle *h) 
		 kinfo->tc_info.num_tc);

	dev_info(priv->dev, "MAX INT QL: %u\n", dev_specs->int_ql_max);

	dev_info(priv->dev, "MAX INT GL: %u\n", dev_specs->max_int_gl);

	dev_info(priv->dev, "MAX frame size: %u\n", dev_specs->max_frm_size);

}



static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+1 −2
Original line number Diff line number Diff line
@@ -4306,8 +4306,7 @@ static int hns3_client_init(struct hnae3_handle *handle) 


	hns3_dbg_init(handle);



	/* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */

	netdev->max_mtu = HNS3_MAX_MTU;

	netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);



	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))

		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);

drivers/net/ethernet/hisilicon/hns3/hns3_enet.h

+2 −3
Original line number Diff line number Diff line
@@ -56,9 +56,8 @@ enum hns3_nic_state { 
#define HNS3_RING_MIN_PENDING			72

#define HNS3_RING_BD_MULTIPLE			8

/* max frame size of mac */

#define HNS3_MAC_MAX_FRAME			9728

#define HNS3_MAX_MTU \

	(HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))

#define HNS3_MAX_MTU(max_frm_size) \

	((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))



#define HNS3_BD_SIZE_512_TYPE			0

#define HNS3_BD_SIZE_1024_TYPE			1

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+2 −1
Original line number Diff line number Diff line
@@ -1131,7 +1131,8 @@ struct hclge_dev_specs_0_cmd { 
#define HCLGE_DEF_MAX_INT_GL		0x1FE0U



struct hclge_dev_specs_1_cmd {

	__le32 rsv0;

	__le16 max_frm_size;

	__le16 rsv0;

	__le16 max_int_gl;

	u8 rsv1[18];

};