Commit 8d4c0d18 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.18-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.18

  - Add MOST (MediaLB I/F) pins on R-Car E3 and D3,
  - Add support for the new RZ/V2L SoC,
  - Miscellaneous fixes and improvements.
parents b8f79acc 2e08ab04

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+12 −4
Original line number Diff line number Diff line
@@ -4,14 +4,14 @@ 
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/G2L combined Pin and GPIO controller

title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO

  The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO

  controller.

  Pin multiplexing and GPIO configuration is performed on a per-pin basis.

  Each port features up to 8 pins, each of them configurable for GPIO function
@@ -20,9 +20,16 @@ description: 


properties:

  compatible:

    enum:

    oneOf:

      - items:

          - enum:

              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}



      - items:

          - enum:

              - renesas,r9a07g054-pinctrl     # RZ/V2L

          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L



  reg:

    maxItems: 1
@@ -76,6 +83,7 @@ additionalProperties: 
        output-impedance-ohms:

          enum: [ 33, 50, 66, 100 ]

        power-source:

          description: I/O voltage in millivolt.

          enum: [ 1800, 2500, 3300 ]

        slew-rate: true

        gpio-hog: true

drivers/pinctrl/renesas/Kconfig

+4 −2
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ config PINCTRL_RENESAS 
	select PINCTRL_PFC_R8A77995 if ARCH_R8A77995

	select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0

	select PINCTRL_RZG2L if ARCH_R9A07G044

	select PINCTRL_RZG2L if ARCH_R9A07G054

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -178,14 +179,15 @@ config PINCTRL_RZA2 
	  This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms.



config PINCTRL_RZG2L

	bool "pin control support for RZ/G2L" if COMPILE_TEST

	bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST

	depends on OF

	select GPIOLIB

	select GENERIC_PINCTRL_GROUPS

	select GENERIC_PINMUX_FUNCTIONS

	select GENERIC_PINCONF

	help

	  This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms.

	  This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L}

	  platforms.



config PINCTRL_PFC_R8A77470

	bool "pin control support for RZ/G1C" if COMPILE_TEST

drivers/pinctrl/renesas/pfc-r8a7779.c

+4 −4
Original line number Diff line number Diff line
@@ -3133,10 +3133,6 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(lbsc),

	SH_PFC_FUNCTION(mmc0),

	SH_PFC_FUNCTION(mmc1),

	SH_PFC_FUNCTION(sdhi0),

	SH_PFC_FUNCTION(sdhi1),

	SH_PFC_FUNCTION(sdhi2),

	SH_PFC_FUNCTION(sdhi3),

	SH_PFC_FUNCTION(scif0),

	SH_PFC_FUNCTION(scif1),

	SH_PFC_FUNCTION(scif2),
@@ -3144,6 +3140,10 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(scif4),

	SH_PFC_FUNCTION(scif5),

	SH_PFC_FUNCTION(scif_clk),

	SH_PFC_FUNCTION(sdhi0),

	SH_PFC_FUNCTION(sdhi1),

	SH_PFC_FUNCTION(sdhi2),

	SH_PFC_FUNCTION(sdhi3),

	SH_PFC_FUNCTION(usb0),

	SH_PFC_FUNCTION(usb1),

	SH_PFC_FUNCTION(usb2),

drivers/pinctrl/renesas/pfc-r8a7790.c

+19 −26
Original line number Diff line number Diff line
@@ -194,24 +194,24 @@ enum { 
	FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,

	FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,

	FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,

	FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,

	FN_WE0_N, FN_IECLK, FN_CAN_CLK,

	FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,

	FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,

	FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,

	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,

	FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,

	FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,

	FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,

	FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,

	FN_SSI_WS78_B,



	/* IPSR6 */

	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,

	FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,

	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,

	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,

	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,

	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,

	FN_SSI_WS6_B, FN_SSI_SDATA8_C,

	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,

	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,

	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,

	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,

	FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,

	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
@@ -568,23 +568,23 @@ enum { 
	CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,

	CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,

	VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,

	INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,

	WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,

	VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,

	WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,

	VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,

	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,

	IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,

	VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,

	MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,

	VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,

	SSI_WS78_B_MARK,



	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,

	DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,

	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,

	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,

	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,

	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,

	SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,

	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,

	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,

	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,

	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,

	ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,

	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
@@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),

	PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),

	PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),

	PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),

	PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),

	PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),

	PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
@@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),

	PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),

	PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),

	PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),

	PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),

	PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),

	PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
@@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP6_2_0, DACK0),

	PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),

	PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),

	PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),

	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),

	PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
@@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),

	PINMUX_IPSR_GPSR(IP6_8_6, DACK1),

	PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),

	PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),

	PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),

	PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),

	PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
@@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),

	PINMUX_IPSR_GPSR(IP6_13_11, DACK2),

	PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),

	PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),

	PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),

	PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),

	PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
@@ -4964,10 +4959,10 @@ static const struct { 
	.common = {

		SH_PFC_FUNCTION(audio_clk),

		SH_PFC_FUNCTION(avb),

		SH_PFC_FUNCTION(du),

		SH_PFC_FUNCTION(can0),

		SH_PFC_FUNCTION(can1),

		SH_PFC_FUNCTION(can_clk),

		SH_PFC_FUNCTION(du),

		SH_PFC_FUNCTION(du0),

		SH_PFC_FUNCTION(du1),

		SH_PFC_FUNCTION(du2),
@@ -5415,9 +5410,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,

		FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,

		/* IP5_26_24 [3] */

		FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,

		FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,

		FN_MSIOF0_SCK_B, 0,

		FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,

		FN_HRX0_B, FN_MSIOF0_SCK_B, 0,

		/* IP5_23_21 [3] */

		FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,

		FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
@@ -5426,7 +5420,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,

		/* IP5_17_15 [3] */

		FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,

		FN_INTC_IRQ4_N, 0, 0,

		0, 0, 0,

		/* IP5_14_13 [2] */

		FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,

		/* IP5_12_10 [3] */
@@ -5467,19 +5461,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,

		FN_I2C2_SCL_E, 0,

		/* IP6_13_11 [3] */

		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,

		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,

		FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,

		FN_MSIOF0_RXD_B, 0, 0,

		/* IP6_10_9 [2] */

		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,

		/* IP6_8_6 [3] */

		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,

		FN_SSI_SDATA8_C, 0, 0, 0,

		FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,

		/* IP6_5_3 [3] */

		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,

		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,

		/* IP6_2_0 [3] */

		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,

		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))

		FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,

		FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))

	},

	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,

			     GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),

drivers/pinctrl/renesas/pfc-r8a7791.c

+15 −20
Original line number Diff line number Diff line
@@ -234,11 +234,11 @@ enum { 
	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,

	FN_SCIFA2_RXD, FN_FMIN_E,

	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,

	FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,

	FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,

	FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,

	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,

	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,

	FN_IRQ0, FN_SCIFB1_RXD_D,

	FN_IRQ1, FN_SCIFB1_SCK_C,

	FN_IRQ2, FN_SCIFB1_TXD_D,

	FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,

	FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,

	FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,

	FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,

	FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
@@ -606,12 +606,12 @@ enum { 
	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,

	SCIFA2_RXD_MARK, FMIN_E_MARK,

	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,

	IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,

	IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,

	IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,

	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,

	IRQ0_MARK, SCIFB1_RXD_D_MARK,

	IRQ1_MARK, SCIFB1_SCK_C_MARK,

	IRQ2_MARK, SCIFB1_TXD_D_MARK,

	IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,

	IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,

	MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,

	MSIOF2_RXD_E_MARK,

	IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,

	IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,

	I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
@@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),

	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),

	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),

	PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),

	PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),

	PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),

	PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),

	PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),

	PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),

	PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),

	PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),

	PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),

	PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),

	PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),

	PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),

	PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),

	PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),

	PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),

	PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),

	PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),

	PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),

	PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
@@ -6033,15 +6028,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,

		/* IP6_18_16 [3] */

		FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,

		FN_INTC_IRQ4_N,	0, 0, 0,

		0, 0, 0, 0,

		/* IP6_15_14 [2] */

		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,

		FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,

		/* IP6_13_12 [2] */

		FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,

		FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,

		/* IP6_11_10 [2] */

		FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,

		FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,

		/* IP6_9_8 [2] */

		FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,

		FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,

		/* IP6_7_6 [2] */

		FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,

		/* IP6_5_3 [3] */