Commit 8d2c749e authored by Yong Wu's avatar Yong Wu Committed by Will Deacon
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iommu/mediatek: Support master use iova over 32bit 



After extending v7s, our pagetable already support iova reach
16GB(34bit). the master got the iova via dma_alloc_attrs may reach
34bits, but its HW register still is 32bit. then how to set the
bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).

we separate whole 16GB iova to four banks:
bank: 0: 0~4G; 1: 4~8G; 2: 8-12G; 3: 12-16G;
The bank number is (iova >> 32).

We will preassign which bank the larbs belong to. currently we don't
have a interface for master to adjust its bank number.

Each a bank is a iova_region which is a independent iommu-domain.
the iova range for each iommu-domain can't cross 4G.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org> #for memory part
Reviewed-by: default avatarTomasz Figa <tfiga@chromium.org>
Link: https://lore.kernel.org/r/20210111111914.22211-31-yong.wu@mediatek.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ab1d5281

drivers/iommu/mtk_iommu.c

+12 −6
Original line number Diff line number Diff line
@@ -345,21 +345,27 @@ static int mtk_iommu_get_domain_id(struct device *dev, 
	return -EINVAL;

}



static void mtk_iommu_config(struct mtk_iommu_data *data,

			     struct device *dev, bool enable)

static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,

			     bool enable, unsigned int domid)

{

	struct mtk_smi_larb_iommu    *larb_mmu;

	unsigned int                 larbid, portid;

	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);

	const struct mtk_iommu_iova_region *region;

	int i;



	for (i = 0; i < fwspec->num_ids; ++i) {

		larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);

		portid = MTK_M4U_TO_PORT(fwspec->ids[i]);



		larb_mmu = &data->larb_imu[larbid];



		dev_dbg(dev, "%s iommu port: %d\n",

			enable ? "enable" : "disable", portid);

		region = data->plat_data->iova_region + domid;

		larb_mmu->bank[portid] = upper_32_bits(region->iova_base);



		dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",

			enable ? "enable" : "disable", dev_name(larb_mmu->dev),

			portid, domid, larb_mmu->bank[portid]);



		if (enable)

			larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
@@ -477,7 +483,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, 
		pm_runtime_put(m4udev);

	}



	mtk_iommu_config(data, dev, true);

	mtk_iommu_config(data, dev, true, domid);

	return 0;

}
@@ -489,7 +495,7 @@ static void mtk_iommu_detach_device(struct iommu_domain *domain, 
	if (!data)

		return;



	mtk_iommu_config(data, dev, false);

	mtk_iommu_config(data, dev, false, 0);

}



static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,

drivers/memory/mtk-smi.c

+7 −0
Original line number Diff line number Diff line
@@ -44,6 +44,10 @@ 
/* mt2712 */

#define SMI_LARB_NONSEC_CON(id)	(0x380 + ((id) * 4))

#define F_MMU_EN		BIT(0)

#define BANK_SEL(id)		({			\

	u32 _id = (id) & 0x3;				\

	(_id << 8 | _id << 10 | _id << 12 | _id << 14);	\

})



/* SMI COMMON */

#define SMI_BUS_SEL			0x220
@@ -88,6 +92,7 @@ struct mtk_smi_larb { /* larb: local arbiter */ 
	const struct mtk_smi_larb_gen	*larb_gen;

	int				larbid;

	u32				*mmu;

	unsigned char			*bank;

};



static int mtk_smi_clk_enable(const struct mtk_smi *smi)
@@ -154,6 +159,7 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 
		if (dev == larb_mmu[i].dev) {

			larb->larbid = i;

			larb->mmu = &larb_mmu[i].mmu;

			larb->bank = larb_mmu[i].bank;

			return 0;

		}

	}
@@ -172,6 +178,7 @@ static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 
	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {

		reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));

		reg |= F_MMU_EN;

		reg |= BANK_SEL(larb->bank[i]);

		writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));

	}

}

include/soc/mediatek/smi.h

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
struct mtk_smi_larb_iommu {

	struct device *dev;

	unsigned int   mmu;

	unsigned char  bank[32];

};



/*