Commit 8d231dbc authored by Maher Sanalla's avatar Maher Sanalla Committed by Saeed Mahameed
Browse files

net/mlx5: Expose shared buffer registers bits and structs 



Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register

Signed-off-by: default avatarMaher Sanalla <msanalla@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent a6f53606

include/linux/mlx5/driver.h

+2 −0
Original line number Diff line number Diff line
@@ -100,6 +100,8 @@ enum { 
};



enum {

	MLX5_REG_SBPR            = 0xb001,

	MLX5_REG_SBCM            = 0xb002,

	MLX5_REG_QPTS            = 0x4002,

	MLX5_REG_QETCR		 = 0x4005,

	MLX5_REG_QTCT		 = 0x400a,

include/linux/mlx5/mlx5_ifc.h

+61 −0
Original line number Diff line number Diff line
@@ -11000,6 +11000,67 @@ struct mlx5_ifc_pbmc_reg_bits { 
	u8         reserved_at_2e0[0x80];

};



struct mlx5_ifc_sbpr_reg_bits {

	u8         desc[0x1];

	u8         snap[0x1];

	u8         reserved_at_2[0x4];

	u8         dir[0x2];

	u8         reserved_at_8[0x14];

	u8         pool[0x4];



	u8         infi_size[0x1];

	u8         reserved_at_21[0x7];

	u8         size[0x18];



	u8         reserved_at_40[0x1c];

	u8         mode[0x4];



	u8         reserved_at_60[0x8];

	u8         buff_occupancy[0x18];



	u8         clr[0x1];

	u8         reserved_at_81[0x7];

	u8         max_buff_occupancy[0x18];



	u8         reserved_at_a0[0x8];

	u8         ext_buff_occupancy[0x18];

};



struct mlx5_ifc_sbcm_reg_bits {

	u8         desc[0x1];

	u8         snap[0x1];

	u8         reserved_at_2[0x6];

	u8         local_port[0x8];

	u8         pnat[0x2];

	u8         pg_buff[0x6];

	u8         reserved_at_18[0x6];

	u8         dir[0x2];



	u8         reserved_at_20[0x1f];

	u8         exc[0x1];



	u8         reserved_at_40[0x40];



	u8         reserved_at_80[0x8];

	u8         buff_occupancy[0x18];



	u8         clr[0x1];

	u8         reserved_at_a1[0x7];

	u8         max_buff_occupancy[0x18];



	u8         reserved_at_c0[0x8];

	u8         min_buff[0x18];



	u8         infi_max[0x1];

	u8         reserved_at_e1[0x7];

	u8         max_buff[0x18];



	u8         reserved_at_100[0x20];



	u8         reserved_at_120[0x1c];

	u8         pool[0x4];

};



struct mlx5_ifc_qtct_reg_bits {

	u8         reserved_at_0[0x8];

	u8         port_number[0x8];