Commit 8cf6f361 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 



- OD fixes for powerplay
- Vega20 fixes
- KFD fix for Kaveri
- add missing firmware declaration for hainan (SI chip)
- Fix DC user experience regressions related to panels that support >8 bpc

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181121163647.2847-1-alexander.deucher@amd.com
parents 1d74f133 a5d0f456

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+5 −2
Original line number Diff line number Diff line
@@ -501,8 +501,11 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;



	if (adev->powerplay.pp_funcs &&

	    adev->powerplay.pp_funcs->switch_power_profile)

		amdgpu_dpm_switch_power_profile(adev,

					PP_SMC_POWER_PROFILE_COMPUTE, !idle);

						PP_SMC_POWER_PROFILE_COMPUTE,

						!idle);

}



bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+7 −0
Original line number Diff line number Diff line
@@ -626,6 +626,13 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 
					 "dither",

					 amdgpu_dither_enum_list, sz);



	if (amdgpu_device_has_dc_support(adev)) {

		adev->mode_info.max_bpc_property =

			drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);

		if (!adev->mode_info.max_bpc_property)

			return -ENOMEM;

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+2 −0
Original line number Diff line number Diff line
@@ -339,6 +339,8 @@ struct amdgpu_mode_info { 
	struct drm_property *audio_property;

	/* FMT dithering */

	struct drm_property *dither_property;

	/* maximum number of bits per channel for monitor color */

	struct drm_property *max_bpc_property;

	/* hardcoded DFP edid from BIOS */

	struct edid *bios_hardcoded_edid;

	int bios_hardcoded_edid_size;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); 
MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");

MODULE_FIRMWARE("amdgpu/verde_mc.bin");

MODULE_FIRMWARE("amdgpu/oland_mc.bin");

MODULE_FIRMWARE("amdgpu/hainan_mc.bin");

MODULE_FIRMWARE("amdgpu/si58_mc.bin");



#define MC_SEQ_MISC0__MT__MASK   0xf0000000

drivers/gpu/drm/amd/amdgpu/soc15.c

+32 −7
Original line number Diff line number Diff line
@@ -65,6 +65,13 @@ 
#define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba

#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0



/* for Vega20 register name change */

#define mmHDP_MEM_POWER_CTRL	0x00d4

#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK	0x00000001L

#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK	0x00000002L

#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK	0x00010000L

#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK		0x00020000L

#define mmHDP_MEM_POWER_CTRL_BASE_IDX	0

/*

 * Indirect registers accessor

 */
@@ -870,6 +877,23 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable 
{

	uint32_t def, data;



	if (adev->asic_type == CHIP_VEGA20) {

		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));



		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))

			data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;

		else

			data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |

				HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);



		if (def != data)

			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);

	} else {

		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));



		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
@@ -880,6 +904,7 @@ static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable 
		if (def != data)

			WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);

	}

}



static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)

{