Commit 8cc8a324 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Turn the MMU-on sequence into a macro 



Turning the MMU on is a popular sport in the arm64 kernel, and
we do it more than once, or even twice. As we are about to add
even more, let's turn it into a macro.

No expected functional change.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Acked-by: default avatarDavid Brazdil <dbrazdil@google.com>
Link: https://lore.kernel.org/r/20210208095732.3267263-4-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b161f924

arch/arm64/include/asm/assembler.h

+17 −0
Original line number Diff line number Diff line
@@ -675,6 +675,23 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
	.endif

	.endm



/*

 * Set SCTLR_EL1 to the passed value, and invalidate the local icache

 * in the process. This is called when setting the MMU on.

 */

.macro set_sctlr_el1, reg

	msr	sctlr_el1, \reg

	isb

	/*

	 * Invalidate the local I-cache so that any instructions fetched

	 * speculatively from the PoC are discarded, since they may have

	 * been dynamically patched at the PoU.

	 */

	ic	iallu

	dsb	nsh

	isb

.endm



/*

 * Check whether to yield to another runnable task from kernel mode NEON code

 * (which runs with preemption disabled).

arch/arm64/kernel/head.S

+4 −15
Original line number Diff line number Diff line
@@ -703,16 +703,9 @@ SYM_FUNC_START(__enable_mmu) 
	offset_ttbr1 x1, x3

	msr	ttbr1_el1, x1			// load TTBR1

	isb

	msr	sctlr_el1, x0

	isb

	/*

	 * Invalidate the local I-cache so that any instructions fetched

	 * speculatively from the PoC are discarded, since they may have

	 * been dynamically patched at the PoU.

	 */

	ic	iallu

	dsb	nsh

	isb



	set_sctlr_el1	x0



	ret

SYM_FUNC_END(__enable_mmu)
@@ -883,11 +876,7 @@ SYM_FUNC_START_LOCAL(__primary_switch) 
	tlbi	vmalle1				// Remove any stale TLB entries

	dsb	nsh



	msr	sctlr_el1, x19			// re-enable the MMU

	isb

	ic	iallu				// flush instructions fetched

	dsb	nsh				// via old mapping

	isb

	set_sctlr_el1	x19			// re-enable the MMU



	bl	__relocate_kernel

#endif

arch/arm64/mm/proc.S

+1 −11
Original line number Diff line number Diff line
@@ -291,17 +291,7 @@ skip_pgd: 
	/* We're done: fire up the MMU again */

	mrs	x17, sctlr_el1

	orr	x17, x17, #SCTLR_ELx_M

	msr	sctlr_el1, x17

	isb



	/*

	 * Invalidate the local I-cache so that any instructions fetched

	 * speculatively from the PoC are discarded, since they may have

	 * been dynamically patched at the PoU.

	 */

	ic	iallu

	dsb	nsh

	isb

	set_sctlr_el1	x17



	/* Set the flag to zero to indicate that we're all done */

	str	wzr, [flag_ptr]