Commit 8c9f215a authored by Yongqiang Niu's avatar Yongqiang Niu Committed by Chun-Kuang Hu
Browse files

drm/mediatek: Add component POSTMASK 



This patch add component POSTMASK.

Signed-off-by: default avatarYongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: default avatarHsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent 787a7a87

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

+72 −30
Original line number Diff line number Diff line
@@ -60,6 +60,12 @@ 
#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)

#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)



#define DISP_POSTMASK_EN			0x0000

#define POSTMASK_EN					BIT(0)

#define DISP_POSTMASK_CFG			0x0020

#define POSTMASK_RELAY_MODE				BIT(0)

#define DISP_POSTMASK_SIZE			0x0030



struct mtk_ddp_comp_dev {

	struct clk *clk;

	void __iomem *regs;
@@ -211,6 +217,32 @@ static void mtk_dither_stop(struct device *dev) 
	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);

}



static void mtk_postmask_config(struct device *dev, unsigned int w,

				unsigned int h, unsigned int vrefresh,

				unsigned int bpc, struct cmdq_pkt *cmdq_pkt)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,

		      DISP_POSTMASK_SIZE);

	mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,

		      priv->regs, DISP_POSTMASK_CFG);

}



static void mtk_postmask_start(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);

}



static void mtk_postmask_stop(struct device *dev)

{

	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);



	writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);

}



static const struct mtk_ddp_comp_funcs ddp_aal = {

	.clk_enable = mtk_aal_clk_enable,

	.clk_disable = mtk_aal_clk_disable,
@@ -286,6 +318,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { 
	.bgclr_in_off = mtk_ovl_bgclr_in_off,

};



static const struct mtk_ddp_comp_funcs ddp_postmask = {

	.clk_enable = mtk_ddp_clk_enable,

	.clk_disable = mtk_ddp_clk_disable,

	.config = mtk_postmask_config,

	.start = mtk_postmask_start,

	.stop = mtk_postmask_stop,

};



static const struct mtk_ddp_comp_funcs ddp_rdma = {

	.clk_enable = mtk_rdma_clk_enable,

	.clk_disable = mtk_rdma_clk_disable,
@@ -321,6 +361,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { 
	[MTK_DISP_MUTEX] = "mutex",

	[MTK_DISP_OD] = "od",

	[MTK_DISP_BLS] = "bls",

	[MTK_DISP_POSTMASK] = "postmask",

};



struct mtk_ddp_comp_match {
@@ -351,6 +392,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { 
	[DDP_COMPONENT_OVL_2L0]		= { MTK_DISP_OVL_2L,	0, &ddp_ovl },

	[DDP_COMPONENT_OVL_2L1]		= { MTK_DISP_OVL_2L,	1, &ddp_ovl },

	[DDP_COMPONENT_OVL_2L2]		= { MTK_DISP_OVL_2L,    2, &ddp_ovl },

	[DDP_COMPONENT_POSTMASK0]	= { MTK_DISP_POSTMASK,	0, &ddp_postmask },

	[DDP_COMPONENT_PWM0]		= { MTK_DISP_PWM,	0, NULL },

	[DDP_COMPONENT_PWM1]		= { MTK_DISP_PWM,	1, NULL },

	[DDP_COMPONENT_PWM2]		= { MTK_DISP_PWM,	2, NULL },

drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { 
	MTK_DISP_UFOE,

	MTK_DSI,

	MTK_DPI,

	MTK_DISP_POSTMASK,

	MTK_DISP_PWM,

	MTK_DISP_MUTEX,

	MTK_DISP_OD,