Commit 8c166acb authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: dsa: felix: directly call ocelot_port_{set,unset}_dsa_8021q_cpu 



Absorb the final details of calling ocelot_port_{,un}set_dsa_8021q_cpu(),
i.e. the need to lock &ocelot->fwd_domain_lock, into the callee, to
simplify the caller and permit easier code reuse later.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a72e23dd

drivers/net/dsa/ocelot/felix.c

+9 −27
Original line number Original line Diff line number Diff line
@@ -240,31 +240,6 @@ static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 
	return 0;

	return 0;

}

}





/* Alternatively to using the NPI functionality, that same hardware MAC

 * connected internally to the enetc or fman DSA master can be configured to

 * use the software-defined tag_8021q frame format. As far as the hardware is

 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port

 * module are now disconnected from it, but can still be accessed through

 * register-based MMIO.

 */

static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port)

{

	mutex_lock(&ocelot->fwd_domain_lock);



	ocelot_port_set_dsa_8021q_cpu(ocelot, port);



	mutex_unlock(&ocelot->fwd_domain_lock);

}



static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port)

{

	mutex_lock(&ocelot->fwd_domain_lock);



	ocelot_port_unset_dsa_8021q_cpu(ocelot, port);



	mutex_unlock(&ocelot->fwd_domain_lock);

}



static int felix_trap_get_cpu_port(struct dsa_switch *ds,

static int felix_trap_get_cpu_port(struct dsa_switch *ds,

				   const struct ocelot_vcap_filter *trap)

				   const struct ocelot_vcap_filter *trap)

{

{
@@ -423,6 +398,13 @@ static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds) 
	return BIT(ocelot->num_phys_ports);

	return BIT(ocelot->num_phys_ports);

}

}





/* Alternatively to using the NPI functionality, that same hardware MAC

 * connected internally to the enetc or fman DSA master can be configured to

 * use the software-defined tag_8021q frame format. As far as the hardware is

 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port

 * module are now disconnected from it, but can still be accessed through

 * register-based MMIO.

 */

static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = {

static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = {

	.setup			= felix_tag_npi_setup,

	.setup			= felix_tag_npi_setup,

	.teardown		= felix_tag_npi_teardown,

	.teardown		= felix_tag_npi_teardown,
@@ -440,7 +422,7 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds) 
		return err;

		return err;





	dsa_switch_for_each_cpu_port(cpu_dp, ds) {

	dsa_switch_for_each_cpu_port(cpu_dp, ds) {

		felix_8021q_cpu_port_init(ocelot, cpu_dp->index);

		ocelot_port_set_dsa_8021q_cpu(ocelot, cpu_dp->index);





		/* TODO we could support multiple CPU ports in tag_8021q mode */

		/* TODO we could support multiple CPU ports in tag_8021q mode */

		break;

		break;
@@ -490,7 +472,7 @@ static void felix_tag_8021q_teardown(struct dsa_switch *ds) 
	}

	}





	dsa_switch_for_each_cpu_port(cpu_dp, ds) {

	dsa_switch_for_each_cpu_port(cpu_dp, ds) {

		felix_8021q_cpu_port_deinit(ocelot, cpu_dp->index);

		ocelot_port_unset_dsa_8021q_cpu(ocelot, cpu_dp->index);





		/* TODO we could support multiple CPU ports in tag_8021q mode */

		/* TODO we could support multiple CPU ports in tag_8021q mode */

		break;

		break;

drivers/net/ethernet/mscc/ocelot.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -2195,6 +2195,8 @@ void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port) 
{

{

	u16 vid;

	u16 vid;





	mutex_lock(&ocelot->fwd_domain_lock);



	ocelot->ports[port]->is_dsa_8021q_cpu = true;

	ocelot->ports[port]->is_dsa_8021q_cpu = true;





	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)

	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
@@ -2203,6 +2205,8 @@ void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port) 
	ocelot_update_pgid_cpu(ocelot);

	ocelot_update_pgid_cpu(ocelot);





	ocelot_apply_bridge_fwd_mask(ocelot, true);

	ocelot_apply_bridge_fwd_mask(ocelot, true);



	mutex_unlock(&ocelot->fwd_domain_lock);

}

}

EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu);

EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu);
@@ -2210,6 +2214,8 @@ void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port) 
{

{

	u16 vid;

	u16 vid;





	mutex_lock(&ocelot->fwd_domain_lock);



	ocelot->ports[port]->is_dsa_8021q_cpu = false;

	ocelot->ports[port]->is_dsa_8021q_cpu = false;





	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)

	for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
@@ -2218,6 +2224,8 @@ void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port) 
	ocelot_update_pgid_cpu(ocelot);

	ocelot_update_pgid_cpu(ocelot);





	ocelot_apply_bridge_fwd_mask(ocelot, true);

	ocelot_apply_bridge_fwd_mask(ocelot, true);



	mutex_unlock(&ocelot->fwd_domain_lock);

}

}

EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu);

EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu);