Commit 8c042949 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL 



AFAICS Bspec has never asked us to switch to TPS1 when *disabling*
DP_TP_CTL. Let's stop doing that in case it confuses something.
We do have to switch before we *enable* DP_TP_CTL, but that
is already being handled correctly.

v2: Do the same for FDI
v3: Rebase

Reviewed-by: Imre Deak <imre.deak@intel.com> #v1
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230308212627.7601-1-ville.syrjala@linux.intel.com
parent 68070b76

drivers/gpu/drm/i915/display/intel_ddi.c

+2 −4
Original line number Diff line number Diff line
@@ -2618,8 +2618,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, 


	if (intel_crtc_has_dp_encoder(crtc_state))

		intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),

			     DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,

			     DP_TP_CTL_LINK_TRAIN_PAT1);

			     DP_TP_CTL_ENABLE, 0);



	/* Disable FEC in DP Sink */

	intel_ddi_disable_fec_state(encoder, crtc_state);
@@ -3140,8 +3139,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 
			wait = true;

		}



		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);

		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;

		dp_tp_ctl &= ~DP_TP_CTL_ENABLE;

		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

drivers/gpu/drm/i915/display/intel_fdi.c

+1 −3
Original line number Diff line number Diff line
@@ -845,9 +845,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, 
		intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));



		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */

		intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),

			     DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,

			     DP_TP_CTL_LINK_TRAIN_PAT1);

		intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);

		intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));



		intel_wait_ddi_buf_idle(dev_priv, PORT_E);