Commit 8bf073ca authored by Bas Nieuwenhuizen's avatar Bas Nieuwenhuizen Committed by Alex Deucher
Browse files

drm/amdgpu: Init GFX10_ADDR_CONFIG for VCN v3 in DPG mode. 



Otherwise tiling modes that require the values form this field
(In particular _*_X) would be corrupted upon video decode.

Copied from the VCN v2 code.

Fixes: 99541f39 ("drm/amdgpu: add mc resume DPG mode for VCN3.0")
Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com>
Signed-off-by: default avatarBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 8651fcb9

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+4 −0
Original line number Diff line number Diff line
@@ -589,6 +589,10 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(

			VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),

			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);



	/* VCN global tiling registers */

	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(

		UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);

}



static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)